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w wm8980 stereo codec with speaker driver and video buffer wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/ pre-production, march 2007, rev 3.1 copyright ? 2007 wolfson microelectronics plc . description the wm8980 is a low power, high quality stereo codec with integrated video buffer designed for portable applications such as multimedia phone, digital still camera or digital camcorder. the device integrates preamps for stereo differential mics, and includes drivers for speakers, headphone and differential or stereo line output. external component requirements are reduced as no separate microphone or headphone amplifiers are required. an integrated video buffer is provided which has programmable gain from 0-6db (6-12db unloaded), sync-tip clamp and a 3 rd order input low pass filter for signal re-construction. advanced on-chip digital signal processing includes a 5-band equaliser, a mixed signal automatic level control for the microphone or line input through the adc as well as a purely digital limiter function for record or playback. additional digital filtering options are available in the adc path, to cater for application filtering such as ?wind noise reduction?. the wm8980 digital audio interface can operate as a master or a slave. an internal pll can generate all required audio clocks for the codec from common reference clock frequencies, such as 12mhz and 13mhz. the wm8980 operates at analogue supply voltages from 2.5v to 3.3v, although the digital core can operate at voltages down to 1.71v to save power. the speaker outputs and out3/4 line outputs can run from a 5v supply if increased output power is required. individual sections of the chip can also be powered down under software control. block diagram features stereo codec: ? dac snr 98db, thd -84db (?a? weighted @ 48khz) ? adc snr 95db, thd -80db (?a? weighted @ 48khz) ? on-chip headphone driver with ?capless? option - 40mw per channel into 16 ? / 3.3v spkvdd ? 0.9w output power into 8 ? btl speaker / 5v spkvdd - capable of driving piezo speakers - stereo speaker drive configuration mic preamps: ? stereo differential or mono microphone interfaces - programmable preamp gain - psuedo differential inputs with common mode rejection - programmable alc / noise gate in adc path ? low-noise bias supplied for electret microphones other features: ? integrated video buffer with lpf filter and clamp. ? enhanced 3-d function for improved stereo separation ? digital playback limiter ? 5-band equaliser (record or playback) ? programmable adc high pass filter (wind noise reduction) ? programmable adc notch filter ? aux inputs for stereo analog input signals or ?beep? ? on-chip pll supporting 12, 13, 19.2mhz and other clocks ? support for 8, 11.025, 12, 16, 22.05, 24, 32, 44.1 and 48khz sample rates ? low power, low voltage - 2.5v to 3.6v (digital: 1.71v to 3.6v) ? 6x6mm 40-lead qfn package applications ? stereo camcorder or dsc ? multimedia phone
wm8980 pre-production w pp rev 3.1 march 2007 2 table of contents description .......................................................................................................1 block diagram .................................................................................................1 features.............................................................................................................1 applications .....................................................................................................1 table of contents .........................................................................................2 pin configuration...........................................................................................4 ordering information ..................................................................................4 pin description ................................................................................................5 absolute maximum ratings.........................................................................6 recommended operating conditions .....................................................6 electrical characteristics ......................................................................7 terminology .......................................................................................................... 10 speaker output thd versus power ......................................................11 power consumption ....................................................................................12 estimating supply current ............................................................................. 12 audio paths overview .................................................................................14 system clock timing ........................................................................................... 15 audio interface timing ? master mode ........................................................ 15 audio interface timing ? slave mode............................................................ 16 control interface timing ? 3-wire mode .................................................... 17 control interface timing ? 2-wire mode .................................................... 18 internal power on reset circuit ..........................................................19 recommended power up/down sequence .................................................. 21 device description .......................................................................................25 introduction ......................................................................................................... 25 input signal path ................................................................................................. 27 analogue to digital converter (adc).......................................................... 35 input limiter / automatic level control (alc) .......................................... 38 output signal path ............................................................................................. 42 3d stereo enhancement .................................................................................... 49 analogue outputs............................................................................................... 49 video buffer .......................................................................................................... 65 digital audio interfaces................................................................................... 69 audio sample rates ............................................................................................. 76 master clock and phase locked loop (pll) ............................................... 76 general purpose input/output...................................................................... 78 output switching (jack detect)..................................................................... 79 control interface.............................................................................................. 81 resetting the chip .............................................................................................. 82 power supplies .................................................................................................... 82 power management ............................................................................................ 83 register map...................................................................................................84 register bits by address ................................................................................. 86 digital filter characteristics .............................................................103 terminology ........................................................................................................ 103 dac filter responses....................................................................................... 104 adc filter responses....................................................................................... 104 highpass filter................................................................................................... 105 5-band equaliser ................................................................................................ 106
pre-production wm8980 w pp rev 3.1 march 2007 3 application information..........................................................................110 recommended external components ........................................................ 110 package diagram ........................................................................................111 important notice ........................................................................................112 address: ................................................................................................................ 112
wm8980 pre-production w pp rev 3.1 march 2007 4 pin configuration ordering information order code temperature range package moisture sensitivity level peak soldering temperature wm8980gefl/v -25 c to +85 c 40-lead qfn (6 x 6 mm) (pb-free) msl3 260 o c wm8980gefl/rv -25 c to +85 c 40-lead qfn (6 x 6 mm) (pb-free, tape and reel) msl3 260 o c note: reel quantity = 3,500
pre-production wm8980 w pp rev 3.1 march 2007 5 pin description pin name type description 1 l2/gpio2 analogue input left channel line input/secondary mic pre-amp positive input/gpio2 pin 2 rip analogue input right mic pre-amp positive input 3 rin analogue input right mic pre-amp negative input 4 r2/gpio3 analogue input right channel line input/secondary mic pre-amp positive input/gpio3 pin 5 vbgnd supply video buffer ground pin 6 vbin analogue input video buffer signal input 7 vbref analogue output video buffer reference resistor pin 8 vbout analogue output video buffer output 9 vbvdd supply video buffer analogue supply 10 nc not internally connected 11 lrc digital input / output dac and adc sample rate clock 12 bclk digital input / output digital audio bit clock 13 adcdat digital output adc digital audio data output 14 dacdat digital input dac digital audio data input 15 mclk digital input master clock input 16 dgnd supply digital ground 17 dcvdd supply digital core logic supply 18 dbvdd supply digital buffer (i/o) supply 19 csb/gpio1 digital input / output 3-wire control interface chip select / gpio1 pin 20 sclk digital input 3-wire control interface clock input / 2-wire control interface clock input 21 sdin digital input / output 3-wire control interface data input / 2-wire control interface data input 22 mode digital input control interface selection 23 gpio4 digital input/output general purpose input/output 4 24 nc not internally connected 25 auxl analogue input left auxillary input 26 auxr analogue input right auxillary input 27 out4 analogue output buffered midrail headphone pseudo-ground, or right line output or mon o mix output 28 out3 analogue output buffered midrail headphone pseudo-ground, or left line output 29 rout2 analogue output second right output, or btl speaker driver negative output 30 spkgnd supply speaker ground (feeds speaker amp and out3/out4) 31 lout2 analogue output second left output, or btl speaker driver positive output 32 spkvdd supply speaker supply (feeds speaker amp only) 33 vmid reference decoupling for adc and dac reference voltage 34 agnd supply analogue ground (feeds adc and dac) 35 rout1 analogue output headphone or line output right 36 lout1 analogue output headphone or line output left 37 avdd supply analogue supply (feeds adc and dac) 38 micbias analogue output microphone bias 39 lip analogue input left mic pre-amp positive input 40 lin analogue input left mic pre-amp negative input note: it is recommended that the qfn ground paddle should be connected to analogue ground on the application pcb.
wm8980 pre-production w pp rev 3.1 march 2007 6 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max dbvdd, dcvdd, avdd, vbvdd s upply voltages -0.3v +4.5v spkvdd supply voltage -0.3v +7v voltage range digital inputs dgnd -0.3v dvdd +0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v operating temperature range, t a -25 c +85 c storage temperature after soldering -65 c +150 c notes 1. analogue and digital grounds must always be within 0.3v of each other. 2. all digital and analogue supplies are completely independent from each other. 3. analogue supply has to be to digital. 4. in non-boosted mode, spkvdd should = avdd, if boosted spkvdd s hould be 1.5x avdd. 5. when using pll, dcvdd should not be 1.9v. recommended operating conditions parameter symbol test conditions min typ max unit digital supply range (core) dcvdd 1.71 1 3.6 v digital supply range (buffer) dbvdd 1.71 3.6 v analogue core supply range avdd 2.5 3.6 v video buffer supply range vbvdd 2.5 3.6 v analogue output supply range spkvdd 2.5 5.5 v ground dgnd,agnd, spkgnd,vbgnd 0 v notes 1. when using the pll, dcvdd must not be less than 1.9v.
pre-production wm8980 w pp rev 3.1 march 2007 7 electrical characteristics test conditions dcvdd=1.8v, avdd=dbvdd=spkvdd=vbvdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit microphone preamp inputs (lip, lin, rip, rin, l2, r2) full-scale input signal level ? note this changes in proportion to avdd (note 1) v infs pgaboost = 0db inppgavol = 0db 1.0 0 vrms dbv mic pga equivalent input noise at 35.25db gain 0 to 20khz 150 uv r micin gain set to 35.25db 1.6 k ? r micin gain set to 0db 47 k ? r micin gain set to -12db 75 k ? r micip l/rip2inppga = 1 94 k ? input resistance c micin 10 pf mic programmable gain amplifier (pga) programmable gain -12 35.25 db programmable gain step size guaranteed monotonic 0.75 db mute attenuation 120 db selectable input gain boost (0/+20db) boost disabled 0 db gain boost on pga input boost enabled 20 db gain range from auxl/r or l/r2 input to boost/mixer -12 +6 db gain step size to boost/mixer 3 db auxilliary analogue inputs (auxl, auxr) full-scale input signal level (0db) ? note this changes in proportion to avdd v infs avdd/3.3 0 vrms dbv r auxinlmin left input boost and mixer enabled, at max gain 4.3 k ? r auxinltyp left input boost and mixer enabled, at 0db gain 8.6 k ? r auxinlmax left input boost and mixer enabled, at min gain 39.1 k ? r auxinrmin right input boost, mixer and beep enabled, at max gain 3 k ? r auxinrtyp right input boost, mixer and beep enabled, at 0db gain 6 k ? input resistance (note 2) r auxinrmax right input boost, mixer and beep enabled, at min gain 29 k ? input capacitance c micin 10 pf
wm8980 pre-production w pp rev 3.1 march 2007 8 test conditions dcvdd=1.8v, avdd=dbvdd=spkvdd=vbvdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit automatic level control (alc) target record level -22.5 -1.5 db programmable gain -12 35.25 gain hold time (note 3,5) t hold mclk = 12.288mhz (note 3) 0, 2.67, 5.33, 10.67, ? , 43691 (time doubles with each step) ms alcmode=0 (alc), mclk=12.288mhz (note 3) 3.3, 6.6, 13.1, ? , 3360 (time doubles with each step) gain ramp-up (decay) time (note 4,5) t dcy alcmode=1 (limiter), mclk=12.288mhz (note 3) 0.73, 1.45, 2.91, ? , 744 (time doubles with each step) ms alcmode=0 (alc), mclk=12.288mhz (note 3) 0.83, 1.66, 3.33, ? , 852 (time doubles with each step) gain ramp-down (attack) time (note 4,5) t atk alcmode=1 (limiter), mclk=12.288mhz (note 3) 0.18, 0.36, 0.73, ? , 186 (time doubles with each step) ms mute attenuation 120 db analogue to digital converter (adc) signal to noise ratio (note 6) snr a-weighted, 0db gain 95 db total harmonic distortion (note 7) thd -3dbfs input -84 db channel separation (note 9) 1khz input signal 110 db digital to analogue converter (dac) to line-out (lout1, rout1 with 10k ? / 50pf load) pga gains set to 0db, out34boost=0 avdd/3.3 full-scale output pga gains set to 0db, out34boost=1 1.5x (avdd/3.3) vrms signal to noise ratio (note 6) snr a-weighted 98 db total harmonic distortion (note 7) thd r l = 10k ? full-scale signal -84 db channel separation (note 8) 1khz signal 110 db output mixers (lmx1, rmx1) pga gain range into mixer -15 0 +6 db pga gain step into mixer 3 db analogue outputs (lout1, rout1, lout2, rout2) programmable gain range -57 0 +6 db programmable gain step size monotonic 1 db mute attenuation 1khz, full scale signal 85 db headphone output (lout1, rout1 with 32 ? load) 0db full scale output voltage avdd/3.3 vrms signal to noise ratio snr a-weighted 102 db r l = 16 ? , po=20mw avdd=3.3v 0.003 -75 % db total harmonic distortion thd r l = 32 ? , po=20mw avdd=3.3v 0.008 - 82 % db
pre-production wm8980 w pp rev 3.1 march 2007 9 test conditions dcvdd=1.8v, avdd=dbvdd=spkvdd=vbvdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit speaker output (lout2, rout2 with 8 ? bridge tied load, invrout2=1) spkboost=0 spkvdd/3.3 vrms full scale output voltage, 0db gain. (note 9) spkboost=1 (spkvdd/3.3)*1.5 output power p o output power is very closely correlated with thd; see below p o =200mw, r l = 8 ? , spkvdd=3.3v 0.04 -68 % db p o =320mw, r l = 8 ? , spkvdd=3.3v 1.0 -40 % db p o =500mw, r l = 8 ? , spkvdd=5v 0.02 -74 % db total harmonic distortion thd p o =860mw, r l = 8 ? , spkvdd=5v 1.0 -40 % db spkvdd=3.3v, r l = 8 ? 90 db signal to noise ratio snr spkvdd=5v, r l = 8 ? 90 db r l = 8 ? btl 80 db power supply rejection ratio (50hz-22khz) psrr r l = 8 ? btl spkvdd=5v ( boost) 69 db out3/out4 outputs (with 10k ? / 50pf load) out3boost=0/ out4boost=0 spkvdd/3.3 vrms full-scale output voltage, 0db gain (note 9) out3boost=1 out4boost=1 (spkvdd/3.3)*1.5 vrms signal to noise ratio (note 6) snr a-weighted 98 db total harmonic distortion (note7) thd r l = 10 k ? full-scale signal -84 db channel separation (note 8) 1khz signal 100 db r l = 10k ? 52 db power supply rejection ratio (50hz-22khz) psrr r l = 10k ? spkvdd=5v ( boost) 56 db microphone bias mbvsel=0 0.9*avdd v bias voltage v micbias mbvsel=1 0.65*avdd v bias current source i micbias 3 ma output noise voltage vn 1k to 20khz 15 nv/ hz video buffer low pass filter order 3 rd order lpf -3db cutoff 10 mhz lpf gain flat to within 0.1db 5.3 mhz maximum output voltage swing vom f=100khz, thd=1% 1.25 vp-p programmable voltage gain av 0 6 db differential gain dg vin=1vp-p 0.3 % differential phase dp vin=1vp-p 0.7 deg signal to noise ratio vsnr +60 db
wm8980 pre-production w pp rev 3.1 march 2007 10 test conditions dcvdd=1.8v, avdd=dbvdd=spkvdd=vbvdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, 24-bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit digital input / output input high level v ih 0.7 dbvdd v input low level v il 0.3 dbvdd v output high level v oh i ol =1ma 0.9 dbvdd v output low level v ol i oh -1ma 0.1xdbvdd v input capacitance tbd pf input leakage tbd pa terminology 1. input level to rip and lip is limited to a maximum of -3db or thd+n performance will be reduced. 2. note when beep path is not enabled then auxl and auxr have the same input impedances. 3. hold time is the length of time between a signal detected being too quiet and beginning to ramp up the gain. it does not apply to ramping down the gain when the signal is too loud, which happens without a delay. 4. ramp-up and ramp-down times are defined as the time it takes for the pga to sweep across 90% of its gain range. 5. all hold, ramp-up and ramp-down times scale proportionally with mclk 6. signal-to-noise ratio (db) ? snr is a measure of the difference in level between the full scale output and the output with no signal applied. (no auto-zero or automute function is employed in achieving these results). 7. thd+n (db) ? thd+n is a ratio, of the rms values, of (noise + distortion)/signal. 8. channel separation (db) ? also known as cross-talk. this is a measure of the amount one channel is isolated from the other. measured by applying a full scale signal to one channel input and measuring the level of signal apparent at the other channel output. 9. the maximum output voltage can be limited by the speaker power supply. if out3boost, out4boost or spkboost is set then s pkvdd s hould be 1.5xavdd to prevent clipping taking place in the output stage (when pga gains are set to 0db).
pre-production wm8980 w pp rev 3.1 march 2007 11 speaker output thd versus power speaker power vs thd+n (8ohm btl load) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.00 50.00 100.00 150.00 200.00 250. 00 300.00 350.00 400.00 450.00 500.00 output power (mw) thd+n (db) avdd=spkvdd=dbvdd=3.3, dcvdd=1.8 speaker power vs thd+n (8ohm btl load) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.00 100.00 200.00 300.00 400.00 500. 00 600.00 700.00 800.00 900.00 1000.00 output power (mw) thd+n (db) avdd=dbvdd=3.3v, spkvdd=5v, dcvdd=1.8v
wm8980 pre-production w pp rev 3.1 march 2007 12 power consumption typical current consumption for various scenarios is shown below. mode avdd (3.0v) (ma) dcvdd (1.9v) (ma) dbvdd 1 (3.0v) (ma) vbvdd (3.0v) (ma) total power (mw) off 0.04 3 0.0008 <0.0001 0 0.12 sleep (vref maintained, no clocks) 0.04 0.0008 <0.0001 0 0.12 mic record (8khz) 2 4.1 1.0 0.001 0 14.1 stereo 16 ? hp playback (48khz, quiescent) 2 3.3 6.2 0.004 0 21.1 stereo 16 ? hp playback (48khz, white noise) 2 5.4 7.3 0.004 0 29.4 stereo 16 ? hp playback (48khz, sine wave) 2 18 6.7 0.004 0 66.1 stereo 16 ? hp playback (48khz, sine wave) 2 video buffer enabled 18 6.7 0.004 4.0 78.1 table 1 power consumption notes: 1. dbvdd current will increase with greater loading on digital i/o pins. 2. 5 band eq is enabled. 3. avdd standby current will fall to nearer 15ua when thermal shutdown sensor is disabled. estimating supply current when either the dac or adc is enabled approximately 7ma will be drawn from dcvdd when dcvdd=1.8v and fs=48khz. when the pll is enabled approximately 1.5ma additional current will be drawn from dcvdd. the video buffer will draw approximately 4ma with no load attached. during normal operation up to 30ma will be drawn. as a general rule, digital supply currents will scale in proportion to sample rates. supply current for analogue and digital blocks will also be lower at lower supply voltages. power consumed by the output drivers will depend greatly on the signal characteristics. a quiet signal, or a signal with long periods of silence will consume less power than a signal which is continuously loud.
pre-production wm8980 w pp rev 3.1 march 2007 13 estimated supply current for the analogue blocks is shown in table 2. note that power dissipated in the load is not shown. register bit avdd current (ma) avdd=3.3v bufdcopen 0.1 out4mixen 0.2 out3mixen 0.2 pllen 1.2 (with clocks applied) micben 0.5 biasen 0.3 bufioen 0.1 vmidsel 0.3 (5k vmid) <0.1 (75k or 300k vmid) rout1en 0.4 lout1en 0.4 boostenr 0.2 boostenl 0.2 inppgaenr 0.2 inppgaenl 0.2 adcenr 2.6 (x64, adcosr=0) 4.9 ( x128, adcosr=1) adcenl 2.6 (x64, adcosr=0) 4.9 ( x128, adcosr=1) out4en 0.2 out3en 0.2 lout2en 1ma from spkvdd + 0.2ma from avdd in 5v m ode rout2en 1ma from spkvdd + 0.2ma from avdd in 5v m ode rmixen 0.2 lmixen 0.2 dacenr 1.8 (x64, dacosr=0) 1.9 (x128, dacosr=1) dacenl 1.8 (x64, dacosr=0) 1.9 (x128, dacosr=1) table 2 avdd supply current (avdd=3.3v)
wm8980 pre-production w pp rev 3.1 march 2007 14 audio paths overview
pre-production wm8980 w pp rev 3.1 march 2007 15 signal timing requirements system clock timing mclk t mclkl t mclkh t mclky figure 1 system clock timing requirements test conditions dcvdd=1.8v, dbvdd=avdd=spkvdd=3.3v, dgnd=agnd=spkgnd=0v, t a = +25 o c parameter symbol conditions min typ max unit system clock timing information mclk=sysclk (=256fs) 81.38 ns mclk cycle time t mclky mclk input to pll note 1 20 ns mclk duty cycle t mclkds 40:60 60:40 note 1: pll pre-scaling and pll n and k values should be set appropriately so that sysclk is no greater t han 12.288mhz. audio interface timing ? master mode 7 figure 2 digital audio data timing ? master mode (see control interface)
wm8980 pre-production w pp rev 3.1 march 2007 16 test conditions dcvdd=1.8v, dbvdd=avdd=spkvdd=3.3v, dgnd=agnd=spkgnd=0v, t a =+25 o c, master mode, fs=48khz, mclk=256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information lrc propagation delay from bclk falling edge t dl 10 ns adcdat propagation delay from bclk falling edge t dda 10 ns dacdat setup time to bclk rising edge t dst 10 ns dacdat hold time from bclk rising edge t dht 10 ns audio interface timing ? slave mode figure 3 digital audio data timing ? slave mode test conditions dcvdd=1.8v, dbvdd=avdd=spkvdd=3.3v, dgnd=agnd=spkgnd=0v, t a =+25 o c, slave mode, fs=48khz, mclk= 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information bclk cycle time t bcy 50 ns bclk pulse width high t bch 20 ns bclk pulse width low t bcl 20 ns lrc set-up time to bclk rising edge t lrsu 10 ns lrc hold time from bclk rising edge t lrh 10 ns dacdat hold time from bclk rising edge t dh 10 ns adcdat propagation delay from bclk falling edge t dd 10 ns note: bclk period should always be greater than or equal to mclk period.
pre-production wm8980 w pp rev 3.1 march 2007 17 control interface timing ? 3-wire mode figure 4 control interface timing ? 3-wire serial control mode test conditions dcvdd = 1.8v, dbvdd = avdd = spkvdd = 3.3v, dgnd = agnd = spkgnd = 0v, t a =+25 o c, slave mode, fs=48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk rising edge to csb rising edge t scs 80 ns sclk pulse cycle time t scy 200 ns sclk pulse width low t scl 80 ns sclk pulse width high t sch 80 ns sdin to sclk set-up time t dsu 40 ns sclk to sdin hold time t dho 40 ns csb pulse width low t csl 40 ns csb pulse width high t csh 40 ns csb rising to sclk rising t css 40 ns pulse width of spikes that will be suppressed t ps 0 5 ns
wm8980 pre-production w pp rev 3.1 march 2007 18 control interface timing ? 2-wire mode sdin sclk t 3 t 1 t 6 t 2 t 7 t 5 t 4 t 3 t 8 t 9 figure 5 control interface timing ? 2-wire serial control mode test conditions dcvdd=1.8v, dbvdd=avdd=spkvdd=3.3v, dgnd=agnd=spkgnd=0v, t a =+25 o c, slave mode, fs=48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk frequency 0 526 khz sclk low pulse-width t 1 1.3 us sclk high pulse-width t 2 600 ns hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sdin, sclk rise time t 6 300 ns sdin, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed t ps 0 5 ns
pre-production wm8980 w pp rev 3.1 march 2007 19 internal power on reset circuit figure 6 internal power on reset circuit schematic the wm8980 includes an internal power-on-reset circuit, as shown in figure 6, which is used reset the digital logic into a default state after power up. the por circuit is powered from avdd and monitors dvdd. it asserts porb low if avdd or dvdd is below a minimum threshold. figure 7 typical power up sequence where avdd is powered before dvdd figure 7 shows a typical power-up sequence where avdd comes up first. when avdd goes above the minimum threshold, v pora , there is enough voltage for the circuit to guarantee porb is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. now avdd is at full supply level. next dvdd rises to v pord_on and porb is released high and all registers are in their default state and writes to the control interface may take place. on power down, where avdd falls first, porb is asserted low whenever avdd drops below the minimum threshold v pora_off .
wm8980 pre-production w pp rev 3.1 march 2007 20 figure 8 typical power up sequence where dvdd is powered before avdd figure 8 shows a typical power-up sequence where dvdd comes up first. first it is assumed that dvdd is already up to specified operating voltage. when avdd goes above the minimum threshold, v pora , there is enough voltage for the circuit to guarantee porb is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. when avdd rises to v pora_on , porb is released high and all registers are in their default state and writes to the control interface may take place. on power down, where dvdd falls first, porb is asserted low whenever dvdd drops below the minimum threshold v pord_off . symbol min typ max unit v pora 0.4 0.6 0.8 v v pora_on 0.9 1.2 1.6 v v pora_off 0.4 0.6 0.8 v v pord_on 0.5 0.7 0.9 v v pord_off 0.4 0.6 0.8 v table 3 typical por operation (typical values, not tested) notes: 1. if avdd and dvdd suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go below v pora_off or v pord_off ) then the chip will not reset and will resume normal operation when the voltage is back to the recommended level again. 2. the chip will enter reset at power down when avdd or dvdd falls below v pora_off or v pord_off . this may be important if the supply is turned on and off frequently by a power management system. 3. the minimum t por period is maintained even if dvdd and avdd have zero rise time. this specification is guaranteed by design rather than test.
pre-production wm8980 w pp rev 3.1 march 2007 21 recommended power up/down sequence in order to minimise output pop and click noise, it is recommended that the wm8980 device is powered up and down using one of the following sequences: power-up when not using the output 1.5x boost stage: 1. turn on external power supplies. wait for supply voltage to settle. 2. mute all analogue outputs. 3. set l/rmixen = 1 and dacenl/r = 1 in register r3. 4. set bufioen = 1 and vmidsel[1:0] to required value in register r1. wait for the vmid supply to settle. *refer notes 1 and 2. 5. set biasen = 1 in register r1. 6. set l/rout1en = 1 in register r2. 7. enable other mixers as required. 8. enable other outputs as required. 9. set remaining registers. power-up when using the output 1.5x boost stage: 1. turn on external power supplies. wait for supply voltage to settle. 2. mute all analogue outputs. 3. enable unused output chosen from l/rout2, out3 or out4. if unused output not available, chose one of these outputs not required at power up. 4. set bufdcopen = 1 and bufioen = 1 in register r1. 5. set spkboost = 1 in register r49. 6. set vmidsel[1:0] to required value in register r1. wait for the vmid supply to settle. *refer notes 1 and 2. 7. set l/rmixen = 1 and dacenl/r = 1 in register r3. 8. set biasen = 1 in register r1. 9. set l/rout2en = 1 in register r3. *note 3. 10. enable other mixers as required. 11. enable other outputs as required. 12. set remaining registers. power down (all cases): 1. mute all analogue outputs. 2. disable power management register 1. r1 = 0x00. 3. disable power management register 2. r2 = 0x00. 4. disable power management register 3. r3 = 0x00. 5. remove external power supplies.
wm8980 pre-production w pp rev 3.1 march 2007 22 notes: 1. this step enables the internal device bias buffer and the vmid buffer for unassigned inputs/outputs. this will provide a startup reference voltage for all inputs and outputs. this will cause the inputs and outputs to ramp towards vmid (not using output 1.5x boost) or 1.5 x (avdd/2) (using output 1.5x boost) in a way that is controlled and predictable (see note 2). 2. choose the value of the vmidsel bits based on the startup time (vmidsel=10 for slowest startup, vmidsel=11 for fastest startup). startup time is defined by the value of the vmidsel bits (the reference impedance) and the external decoupling capacitor on vmid. 3. setting dacen to off while operating in x1.5 boost mode will cause the vmid voltage to drop to avdd/2 midrail level and cause an output pop. in addition to the power on sequence, it is recommended that the zero cross functions are used when changing the volume in the pgas to avoid any audible pops or clicks. v pora dgnd internal por active device ready no power v por_off power supply por i 2 s clocks adc internal state t midrail_on analogue inputs adcdat pin gd adcen bit power down init normal operation normal operation init pd power down adc enabled adc enabled adc off t adcint dnc inppgaen bit t adcint inppga enabled dnc gd gd gd por por undefined vmid enabled vmidsel/ biasen bits avdd/2 t midrail_off (note 1) (note 2) (note 3) (note 4) v por_on figure 9 adc power up and down sequence (not to scale) symbol min typical max unit t midrail_on 500 ms t midrail_off >10 s t adcint 2/fs n /fs adc group delay 29/fs n /fs table 4 typical por operation (typical values, not tested)
pre-production wm8980 w pp rev 3.1 march 2007 23 notes: 1. the analogue input pin charge time, t midrail_on, is determined by the vmid pin charge time. this time is dependent upon the value of vmid decoupling capacitor and vmid pin input resistance and avdd power supply rise time. 2. the analogue input pin discharge time, t midrail_off, is determined by the analogue input coupling capacitor discharge time. the time, t midrail_off , is measured using a 1 f capacitor on the analogue input but will vary dependent upon the value of input coupling capacitor. 3. while the adc is enabled there will be lsb data bit activity on the adcdat pin due to system noise but no significant digital output will be present. 4. the vmidsel and bi asen bits must be set to enable analogue input midrail voltage and for normal adc operation. 5. adcdat data output delay from power up - with power supplies starting from 0v - is determined primarily by the vmid charge time. adc initialisation and power management bits may be set immediately after por is released; vmid charge time will be significantly longer and will dictate when the device is stabilised for analogue input. 6. adcdat data output delay at power up from device standby (power supplies already applied) is determined by adc initialisation time, 2/fs. figure 10 dac power up and down sequence (not to scale)
wm8980 pre-production w pp rev 3.1 march 2007 24 symbol min typical max unit t line_midrail_on 500 ms t line_midrail_off 1 s t hp_midrail_on 500 ms t hp__midrail_off 6 s t dacint 2/fs n /fs dac group delay 29/fs n /fs table 5 typical por operation (typical values, not tested) notes: 1. the lineout charge time, t line_midrail_on, is mainly determined by the vmid pin charge time. this time is dependent upon the value of vmid decoupling capacitor and vmid pin input resistance and avdd power supply rise time. the values above were measured using a 4.7 f capacitor. 2. it is not advisable to allow dacdat data input during initialisation of the dac. if the dac data value is not zero at point of initialisation, then this is likely to cause a pop noise on the analogue outputs. the same is also true if the dacdat is removed at a non-zero value, and no mute function has been applied to the signal beforehand. 3. the lineout discharge time, t line_midrail_off, is dependent upon the value of the lineout coupling capacitor and the leakage resistance path to ground. the values above were measured using a 10 f output capacitor. 4. the headphone charge time, t hp_midrail_on, is dependent upon the value of vmid decoupling capacitor and vmid pin input resistance and avdd power supply rise time. the values above were measured using a 4.7 f vmid decoupling capacitor. 5. the headphone discharge time, t hp_midrail_off, is dependent upon the value of the headphone coupling capacitor and the leakage resistance path to ground. the values above were measured using a 100 f capacitor. 6. the vmidsel and biasen bits must be set to enable analogue output midrail voltage and for normal dac operation.
pre-production wm8980 w pp rev 3.1 march 2007 25 device description introduction the wm8980 is a low power audio codec combining a high quality stereo audio dac and adc, with flexible line and microphone input and output processing. applications for this device include multimedia phones, stereo digital camcorders, and digital still cameras with either mono or stereo, audio and video, record and playback capability. the integrated video buffer makes the device suitable for driving both audio and video signals directly to a television or vcr. features the chip offers great flexibility in use, and so can support many different modes of operation as follows: microphone inputs two pairs of stereo microphone inputs are provided, allowing a pair of stereo microphones to be pseudo-differentially connected, with user defined gain using internal resistors. the provision of the common mode input pin for each stereo input allows for rejection of common mode noise on the microphone inputs (level depends on gain setting chosen). a microphone bias is output from the chip which can be used to bias both microphones. the signal routing can be configured to allow manual adjustment of mic levels, or to allow the alc loop to control the level of mic signal that is transmitted. total gain through the microphone paths of up to +55.25db can be selected. pga and alc operation a programmable gain amplifier is provided in the input path to the adc. this may be used manually or in conjunction with a mixed analogue/digital automatic level control (alc) which keeps the recording volume constant. line inputs (auxl, auxr) the inputs, auxl and auxr, can be used as a stereo line input or as an input for warning tones (or ?beeps?) etc. these inputs can be summed into the record paths, along with the microphone preamp outputs, so allowing for mixing of audio with ?backing music? etc as required. adc the stereo adc uses a 24-bit delta sigma oversampling architecture to deliver optimum performance with low power consumption. hi-fi dac the hi-fi dac provides high quality audio playback suitable for all portable audio hi-fi type applications, including mp3 players and portable disc players of all types. output mixers flexible mixing is provided on the outputs of the device. a stereo mixer is provided for the stereo headphone or line outputs, lout1/rout1, and additional summers on the out3/out4 outputs allow for an optional differential or stereo line output on these pins. gain adjustment pgas are provided for the lout1/rout1 and lout2/rout2 outputs, and signal switching is provided to allow for all possible signal combinations. the output buffers can be configured in several ways, allowing support of up to three sets of external transducers; ie stereo headphone, btl speaker, and btl earpiece may be connected simultaneously. thermal implications should be considered before simultaneous full power operation of all outputs is attempted. alternatively, if a speaker output is not required, the lout2 and rout2 pins might be used as a stereo headphone driver, (disable output invert buffer on rout2). in that case two sets of headphones might be driven, or the lout2 and rout2 pins used as a line output driver.
wm8980 pre-production w pp rev 3.1 march 2007 26 out3 and out4 can be configured to provide an additional stereo lineout from the output of the dacs, the mixers or the input microphone boost stages. alternatively out4 can be configured as a mono mix of left and right dacs or mixers, or simply a buffered version of the chip midrail reference voltage. out3 can also be configured as a buffered vmid output. this voltage may then be used as a headphone ?pseudo ground? allowing removal of the large ac coupling capacitors often used in the output path. audio interfaces the wm8980 has a standard audio interface, to support the transmission of stereo data to and from the chip. this interface is a 3 wire standard audio interface which supports a number of audio data formats including i2s, dsp/pcm mode (a burst mode in which lrc sync plus 2 data packed words are transmitted), msb-first, left justified and msb-first, right justified, and can operate in master or slave modes. control interfaces to allow full software control over all features, the wm8980 offers a choice of 2 or 3 wire control interface. it is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and dsps. selection between the modes is via the mode pin. in 2 wire mode the address of the device is fixed as 0011010. clocking schemes wm8980 offers the normal audio dac clocking scheme operation, where 256fs mclk is provided to the dac and adc. a pll is included which may be used to generate these clo cks in the event that they are not available from the system controller. this pll uses an input clock, typically the 12mhz usb or ilink clock, to generate high quality audio clocks. if this pll is not required for generation of these clocks, it can be reconfigured to generate alternative clo cks which may t hen be output on the gpio pins and used elsewhere in the system. video buffer the wm8980 incorporates a current mode output video buffer with an input 3 rd order low pass filter (lpf) and clamp. the gain through this buffer can be programmed as 0db or 6db via the control interface. the current mode output means that the signal swing seen at the output of the buffer will be the same as that at the connection to the receiving equipment (e.g. a tv). note that the input to the receiver should be ac coupled and terminated to 75 ? , as is standard, for best performance. power control the design of the wm8980 has given much attention to power consumption without compromising performance. it operates at very low voltages, and includes the ability to power off any unused parts of the circuitry under software control, and includes standby and power off modes. operation scenarios flexibility in the design of the wm8980 allows for a wide range of operational scenarios, some of which are proposed below: multimedia phone; high quality playback to a stereo headset, a mono ear speaker or a loudspeaker is supported, allowing hi-fi playback to be mixed with voice and other analogue inputs while simultaneously transmitting a differential output from the microphone amplifier. a 5-band eq enables hi-fi playback to be customised to suit the user's preferences and the music style, while programmable filtering allows fixed-frequency noise (e.g. 217hz) to be reduced in the digital domain. video playback directly to tv is supported using the integrated video buffer.
pre-production wm8980 w pp rev 3.1 march 2007 27 stereo camcorder; the provision of two stereo microphone preamplifiers, allows support for both internal and external microphones. all drivers for speaker, headphone and line output connections are integrated. the selectable ?application filters? after the adc provide for features such as ?wind noise? reduction, or mechanical noise reducing filters. the integrated video buffer allows direct connection to a tv or vcr for both video and audio (via line outputs). stereo digital still camera recording; support for digital stereo video with audio recording is similar to the camcorder case. but additionally if the dsc supports mp3 playback, and perhaps recording, the ability of the adcs to support full 48ks/s high quality stereo recording increases device flexibility. the integrated video buffer allows direct connection to the tv for display of moving and still images. mono digital still camera; full control over device functionality, and power control is provided, allowing for the case of mono dsc recording, when half of the adc and mic and line functionality may be disabled to save power. in the mono case, the single adc channel of audio data is sent out over both left and right channels of the audio interface when normal i2s type interface format is used. in the case where dsp mode is used, and mono data is being sent, only the signal channel of mono data is sent. the integrated video buffer allows direct connection to the tv for display of moving and still images. auxiliary analogue inputs an analogue stereo fm tuner or other auxiliary analogue input can be connected to the line inputs of wm8980, and the stereo signal listened to via headphones, or recorded, simultaneously if required. input signal path the wm8980 has a number of flexible analogue inputs. there are two input channels, left and right, each of which consists of an input pga stage followed by a boost/mix stage which drives into the hi-fi adc. each input path has three input pins which can be configured in a variety of ways to accommodate single-ended, differential or dual differential microphones. there are two auxiliary input pins which can be fed into to the input boost/mix stage as well as driving into the output path. a bypass path exists from the output of the boost/mix stage into the output left/right mixers. microphone inputs the wm8980 can accommodate a variety of microphone configurations including single ended and differential inputs. the inputs to the left differential input pga are lin, lip and l2. the inputs to the right differential input pga are rin, rip and r2. in single-ended microphone input configuration the microphone signal should be input to lin or rin and the internal nor gate configured to clamp the non-inverting input of the input pga to vmid. in differential mode the larger signal should be input to lip or rip and the smaller (e.g. noisy ground connection) should be input to lin or rin. figure 11 microphone input pga circuit
wm8980 pre-production w pp rev 3.1 march 2007 28 the input pgas are enabled by the ippgaenl/r register bits. register address bit label default description 2 inppgaenl 0 left channel input pga enable 0 = disabled 1 = enabled r2 power management 2 3 inppgaenr 0 right channel input pga enable 0 = disabled 1 = enabled table 6 input pga enable register settings register address bit label default description 0 lip2inppga 1 connect lip pin to left channel input pga amplifier positive terminal. 0 = lip not connected to input pga 1 = input pga amplifier positive terminal connected to lip (constant input impedance) 1 lin2inppga 1 connect lin pin to left channel input pga negative terminal. 0=lin not connected to input pga 1=lin connected to input pga amplifier negative terminal. 2 l2_2inppga 0 connect l2 pin to left channel input pga positive terminal. 0=l2 not connected to input pga 1=l2 connected to input pga amplifier positive terminal (constant input impedance). 4 rip2inppga 1 connect rip pin to right channel input pga amplifier positive terminal. 0 = rip not connected to input pga 1 = right channel input pga amplifier positive terminal connected to rip (constant input impedance) 5 rin2inppga 1 connect rin pin to right channel input pga negative terminal. 0=rin not connected to input pga 1=rin connected to right channel input pga amplifier negative terminal. r44 input control 6 r2_2inppga 0 connect r2 pin to right channel input pga positive terminal. 0=r2 not connected to input pga 1=r2 connected to input pga amplifier positive terminal (constant input impedance). table 7 input pga control input pga volume controls the input microphone pgas have a gain range from -12db to +35.25db in 0.75db steps. the gain from the lin/rin input to the pga output and from the l2/r2 amplifier to the pga output are always common and controlled by the register bits inppgavoll/r[5:0]. these register bits also affect the lip pin when lip2inppga=1, the l2 pin when l2_2inppga=1, the rip pin when rip2inppga=1 and the l2 pin when l2_2inppga=1. when the automatic level control (alc) is enabled the input pga gains are controlled automatically and the inppgavoll/r bits should not be used.
pre-production wm8980 w pp rev 3.1 march 2007 29 register address bit label default description 5:0 inppgavoll 010000 left channel input pga volume 000000 = -12db 000001 = -11.25db . 010000 = 0db . 111111 = 35.25db 6 inppgamutel 0 mute control for left channel input pga: 0=input pga not muted, normal operation 1=input pga muted (and disconnected from the following input boost stage). 7 inppgazcl 0 left channel input pga zero cross enable: 0=update gain when gain register changes 1=update gain on 1 st zero cross after gain register write. r45 left channel input pga volume control 8 inppgaupdate not latched inppgavoll and inppgavolr volume do not update until a 1 is written to inppgaupdate (in reg 45 or 46) 5:0 inppgavolr 010000 right channel input pga volume 000000 = -12db 000001 = -11.25db . 010000 = 0db . 111111 = +35.25db 6 inppgamuter 0 mute control for right channel input pga: 0=input pga not muted, normal operation 1=input pga muted (and disconnected from the following input boost stage). 7 inppgazcr 0 right channel input pga zero cross enable: 0=update gain when gain register changes 1=update gain on 1 st zero cross after gain register write. r46 right channel input pga volume control 8 inppgaupdate not latched inppgavoll and inppgavolr volume do not update until a 1 is written to inppgaupdate (in reg 45 or 46) r32 alc control 1 8:7 alcsel 00 alc function select: 00=alc off 01=alc right only 10=alc left only 11=alc both on table 8 input pga volume control
wm8980 pre-production w pp rev 3.1 march 2007 30 volume updates volume settings will not be applied to the pgas until a '1' is written to one of the inppgaupdate bits. this is to allow left and right channels to be updated at the same time, as shown in figure 12. figure 12 simultaneous left and right volume updates if the volume is adjusted while the signal is a non-zero value, an audible click can occur as shown in figure 13. figure 13 click noise during volume update in order to prevent this click noise, a zero cross function is provided. when enabled, this will cause the pga volume to update only when a zero crossing occurs, minimising click noise as shown in figure 14.
pre-production wm8980 w pp rev 3.1 march 2007 31 figure 14 volume update using zero cross detection if there is a long period where no zero-crossing occurs, a timeout circuit in the wm8980 will automatically update the volume. the volume updates will occur between one and two timeout periods, depending on when the inppgaupdate bit is set as shown in figure 15. figure 15 volume update after timeout
wm8980 pre-production w pp rev 3.1 march 2007 32 auxilliary inputs there are two auxilliary inputs, auxl and auxr which can be used for a variety of purposes such as stereo line inputs or as a ?beep? input signal to be mixed with the outputs. the auxl/r inputs can be used as a line input to the input boost stage which has gain adjust of - 12db to +6db in 3db steps (plus off). see the input boost section for further details. the auxl/r inputs can also be mixed into the output channel mixers, with a gain of -15db to +6db plus off. in addition the auxr input can be summed into the right speaker output path (rout2) with a gain adjust of -15 to +6db. this allows a ?beep? input to be output on the speaker outputs only without affecting the headphone or lineout signals. input boost each of the stereo input pga stages is followed by an input boost circuit. the input boost circuit has 3 selectable inputs: the input microphone pga output, the aux amplifier output and the l2/r2 input pin (can be used as a line input, bypassing the input pga). these three inputs can be mixed together and have individual gain boost/adjust as shown in figure 16. figure 16 input boost stage the input pga paths can have a +20db boost (pgaboostl/r=1) , a 0db pass through (pgaboostl/r=0) or be completely isolated from the input boost circuit (inppgamutel/r=1). register address bit label default description r47 left input boost control 8 pgaboostl 1 boost enable for left channel input pga: 0 = pga output has +0db gain through input boost stage. 1 = pga output has +20db gain through input boost stage. r48 right input boost control 8 pgaboostr 1 boost enable for right channel input pga: 0 = pga output has +0db gain through input boost stage. 1 = pga output has +20db gain through input boost stage. table 9 input boost stage control
pre-production wm8980 w pp rev 3.1 march 2007 33 the auxilliary amplifier path to the boost stages is controlled by the auxl2boostvol[2:0] and auxr2boostvol[2:0] register bits. when auxl2boostvol/auxr2boostvol=000 this path is completely disconnected from the boost stage. settings 001 through to 111 control the gain in 3db steps from -12db to +6db. the l2/r2 path to the boost stage is controlled by the lip2boostvol[2:0] and the rip2boostvol[2:0] register bits. when l2_2boostvol/r2_2boostvol=000 the l2/r2 input pin is completely disconnected from the boost stage. settings 001 through to 111 control the gain in 3db steps from -12db to +6db. register address bit label default description 2:0 auxl2boostvol 000 controls the auxilliary amplifer to the left channel input boost stage: 000=path disabled (disconnected) 001=-12db gain through boost stage 010=-9db gain through boost stage ? 111=+6db gain through boost stage r47 left channel input boost control 6:4 l2_2boostvol 000 controls the l2 pin to the left channel input boost stage: 000=path disabled (disconnected) 001=-12db gain through boost stage 010=-9db gain through boost stage ? 111=+6db gain through boost stage 2:0 auxr2boostvol 000 controls the auxilliary amplifer to the right channel input boost stage: 000=path disabled (disconnected) 001=-12db gain through boost stage 010=-9db gain through boost stage ? 111=+6db gain through boost stage r48 right channel input boost control 6:4 r2_2boostvol 000 controls the r2 pin to the right channel input boost stage: 000=path disabled (disconnected) 001=-12db gain through boost stage 010=-9db gain through boost stage ? 111=+6db gain through boost stage table 10 input boost stage control
wm8980 pre-production w pp rev 3.1 march 2007 34 the boost stage is enabled under control of the boosten register bit. register address bit label default description 4 boostenl 0 left channel input boost enable 0 = boost stage off 1 = boost stage on r2 power management 2 5 boostenr 0 right channel input boost enable 0 = boost stage off 1 = boost stage on table 11 input boost enable control microphone biasing circuit the micbias output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. refer to the applications information section for recommended external components. the micbias voltage can be altered via the mbvsel register bit. w hen m bvsel=0, micbias=0.9*avdd and when mbvsel=1, micbias=0.65*avdd. the output can be enabled or disabled using the micben control bit. register address bit label default description r1 power management 1 4 micben 0 microphone bias enable 0 = off (high impedance output) 1 = on table 12 microphone bias enable control register address bit label default description r44 input control 8 mbvsel 0 microphone bias voltage control 0 = 0.9 * avdd 1 = 0.65 * avdd table 13 microphone bias voltage control the internal micbias circuitry is shown in figure 17. note that the maximum source current capability for micbias is 3ma. the external biasing resistors therefore must be large enough to limit the micbias current to 3ma. figure 17 microphone bias schematic
pre-production wm8980 w pp rev 3.1 march 2007 35 analogue to digital converter (adc) the wm8980 uses stereo multi-bit, oversampled sigma-delta adcs. the use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. the adc full scale input level is proportional to avdd. with a 3.3v supply voltage, the full scale level is 1.0v rms . any voltage greater than full scale may overload the adc and cause distortion. adc digital filters the adc filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the adc to the correct sampling frequency to be output on the digital audio interface. the digital filter path for each adc channel is illustrated in figure 18. figure 18 adc digital filter path the adcs are enabled by the adcenl/r register bit. register address bit label default description 0 adcenl 0 enable adc left channel: 0 = adc disabled 1 = adc enabled r2 power management 2 1 adcenr 0 enable adc right channel: 0 = adc disabled 1 = adc enabled table 14 adc enable control the polarity of the output signal can also be changed under software control using the adclpol/adcrpol register bit. the oversampling rate of the adc can be adjusted using the adcosr register bit. with adcosr=0 the oversample rate is 64x which gives lowest power operation and when adcosr=1 the oversample rate is 128x which gives best performance. register address bit label default description 0 adclpol 0 adc left channel polarity adjust: 0=normal 1=inverted 1 adcrpol 0 adc right channel polarity adjust: 0=normal 1=inverted r14 adc control 3 adcosr 0 adc oversample rate select: 0=64x (lower power) 1=128x (best performance) table 15 adc control
wm8980 pre-production w pp rev 3.1 march 2007 36 selectable high pass filter a selectable high pass filter is provided. to disable this filter set hpfen=0. the filter has two modes controlled by hpfapp. in audio mode (hpfapp=0) the filter is first order, with a cut-off frequency of 3.7hz. in application mode (hpfapp=1) the filter is second order, with a cut-off frequency selectable via the hpfcut register. the cut-off frequencies when hpf app=1 are shown in table 17. register address bit label default description 8 hpfen 1 high pass filter enable 0=disabled 1=enabled 7 hpfapp 0 select audio mode or application mode 0=audio mode (1 st order, fc = ~3.7hz) 1=application mode (2 nd order, fc = hpfcut) r14 adc control 6:4 hpfcut 000 application mode cut-off frequency see table 17 for details. table 16 adc enable control sr=101/100 sr=011/010 sr=001/000 fs (khz) hpfcut [2:0] 8 11.025 12 16 22.05 24 32 44.1 48 000 82 113 122 82 113 122 82 113 122 001 102 141 153 102 141 153 102 141 153 010 131 180 156 131 180 156 131 180 156 011 163 225 245 163 225 245 163 225 245 100 204 281 306 204 281 306 204 281 306 101 261 360 392 261 360 392 261 360 392 110 327 450 490 327 450 490 327 450 490 111 408 563 612 408 563 612 408 563 612 table 17 high pass filter cut-off frequencies (hpfapp=1). values in hz. note that the high pass filter values (when hpf app=1) are calculated with the assumption that the sr register bits are set correctly for the actual sample rate as shown in table 17.
pre-production wm8980 w pp rev 3.1 march 2007 37 programmable notch filter a programmable notch filter is provided. this filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. a0 and a1 are represented by the register bits nfa0[13:0] and nfa1[13:0]. because these coefficient values require four register writes to setup there is an nfu (notch filter update) flag which should be set only when all four registers are setup. register address bit label default description 6:0 nfa0[13:7] 0 notch filter a0 coefficient, bits [13:7] 7 nfen 0 notch filter enable: 0=disabled 1=enabled r27 notch filter 1 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. 6:0 nfa0[6:0] 0 notch filter a0 coefficient, bits [6:0] r28 notch filter 2 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. 6:0 nfa1[13:7] 0 notch filter a1 coefficient, bits [13:7] r29 notch filter 3 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. 0-6 nfa1[6:0] 0 notch filter a1 coefficient, bits [6:0] r30 notch filter 4 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. table 18 notch filter function the coefficients are calculated as follows: ) 2 / tan( 1 ) 2 / tan( 1 0 b b w w a + ? = ) cos( ) 1 ( 0 0 1 w a a + ? = where: s c f f w / 2 0 = s b b f f w / 2 = f c = centre frequency in hz, f b = -3db bandwidth in hz, f s = sample frequency in hz the actual register values can be determined from the coefficients as follows: nfa0 = -a0 x 2 13 nfa1 = -a1 x 2 12 digital adc volume control the output of the adcs can be digitally attenuated over a range from ?127db to 0db in 0.5db steps. the gain for a given eight-bit code x is given by: 0.5 (g-255) db for 1 g 255; mute for g = 0
wm8980 pre-production w pp rev 3.1 march 2007 38 register address bit label default description 7:0 adcvoll [7:0] 11111111 ( 0db ) left adc digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db r15 left channel adc digital volume 8 adcvu not latched adc left and adc right volume do not update until a 1 is written to adcvu (in reg 15 or 16) 7:0 adcvolr [7:0] 11111111 ( 0db ) right adc digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db r16 right channel adc digital volume 8 adcvu not latched adc left and adc right volume do not update until a 1 is written to adcvu (in reg 15 or 16) table 19 adc digital volume control input limiter / automatic level control (alc) the wm8980 has an automatic pga gain control circuit, which can function as an input peak limiter or as an automatic level control (alc). in input peak limiter mode (alcmode bit = 1), a digital peak detector detects when the input signal goes above a predefined level and will ramp the pga gain down to prevent the signal becoming too large for the input range of the adc. when the signal returns to a level below the threshold, the pga gain is slowly returned to its starting level. the peak limiter cannot increase the pga gain above its static level. figure 19 input peak limiter operation
pre-production wm8980 w pp rev 3.1 march 2007 39 in alc mode (alcmode bit = 0) the circuit aims to keep a constant recording volume irrespective of the input signal level. this is achieved by continuously adjusting the pga gain so that the signal level at the adc input remains constant. a digital peak detector monitors the adc output and changes the pga gain if necessary. figure 20 alc operation the alc/limiter function is enabled by setting the register bit alcsel. when enabled, the recording volume can be programmed between ?6db and ?28.5db (relative to adc full scale) using the alclvl register bits. an upper limit for the pga gain can be imposed by setting the alcmaxgain control bits and a lower limit for the pga gain can be imposed by setting the alcmingain control bits. alchld, alcdcy and alcatk control the hold, decay and attack times, respectively: hold time is the time delay between the peak level detected being below target and the pga gain beginning to ramp up. it can be programmed in power-of-two (2 n ) steps, e.g. 2.67ms, 5.33ms, 10.67ms etc. up to 43.7s. alternatively, the hold time can also be set to zero. the hold time is not active in limiter mode (alcmode = 1). the hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is above target. decay (gain ramp-up) time is the time that it takes for the pga gain to ramp up and is given as a time per gain step, time per 6db change and time to ramp up over 90% of it?s range. the decay time can be programmed in power-of-two (2 n ) steps, from 3.3ms/6db, 6.6ms/6db, 13.1ms/6db, etc. to 3.36s/6db. attack (gain ramp-down) time is the time that it takes for the pga gain to ramp down and is given as a time per gain step, time per 6db change and time to ramp down over 90% of it?s range. the attack time can be programmed in power-of-two (2 n ) steps, from 832us/6db, 1.66ms/6db, 3.328us/6db, etc. to 852ms/6db. nb, in peak limiter mode the gain control circuit runs approximately 4x faster to allow reduction of fast peaks. attack and decay times for peak limiter mode are given below.
wm8980 pre-production w pp rev 3.1 march 2007 40 the hold, decay and attack times given in table 20 are constant across sample rates so long as the sr bits are set correctly. e.g. when sampling at 48khz the sample rates stated in table 20 will only be correct if the sr bits are set to 000 (48khz). if the actual sample rate was only 44.1khz then the hold, decay and attack times would be scaled down by 44.1/48. register address bit label default description 8:7 alcsel 00 alc function select: 00=alc off 01=alc right only 10=alc left only 11=alc both on 5:3 alcmaxgain [2:0] 111 (+35.25db) set maximum gain of pga 111=+35.25db 110=+29.25db 101=+23.25db 100=+17.25db 011=+11.25db 010=+5.25db 001=-0.75db 000=-6.75db r32 alc control 1 2:0 alcmingain [2:0] 000 (-12db) set minimum gain of pga 000=-12db 001=-6db 010=0db 011=+6db 100=+12db 101=+18db 110=+24db 111=+30db 7:4 alchld [3:0] 0000 (0ms) alc hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ? (time doubles with every step) 1111 = 43.691s r33 alc control 2 3:0 alclvl [3:0] 1011 (-6db) alc target ? sets signal level at adc input 1111 : -1.5dbfs 1110 : -1.5dbfs 1101 : -3dbfs 1100 : -4.5dbfs ...... (-1.5db steps) 0001 : -21dbfs 0000 : -22.5dbfs
pre-production wm8980 w pp rev 3.1 march 2007 41 8 alcmode 0 determines the alc mode of operation: 0=alc mode 1=limiter mode decay (gain ramp-up) time (alcmode ==0) per step per 6db 90% of range 0000 410us 3.3ms 24ms 0001 820us 6.6ms 48ms 0010 1.64ms 13.1ms 192ms ? (time doubles with every step) 0011 (13ms/6db) 1010 or higher 420ms 3.36s 24.576s decay (gain ramp-up) time (alcmode ==1) per step per 6db 90% of range 0000 90.8us 726.4us 5.26ms 0001 181.6us 1.453ms 10.53ms 0010 363.2us 2.905ms 21.06ms ? (time doubles with every step) 7:4 alcdcy [3:0] 0011 (2.9ms/6db) 1010 93ms 744ms 5.39s alc attack (gain ramp-down) time (alcmode == 0) per step per 6db 90% of range 0000 104us 832us 6ms 0001 208us 1.664ms 12ms 0010 416us 3.328ms 24.1ms ? (time doubles with every step) 0010 (832us/6db) 1010 or higher 106ms 852ms 6.18s alc attack (gain ramp-down) time (alcmode == 1) per step per 6db 90% of range 0000 22.7us 182.4us 1.31ms 0001 45.4us 363.2us 2.62ms 0010 90.8us 726.4us 5.26ms ? (time doubles with every step) r34 alc control 3 3:0 alcatk [3:0] 0010 (182us/6db) 1010 23.2ms 186ms 1.348s table 20 alc control registers when the alc is disabled, the input pga remains at the last controlled value of the alc. an input gain update must be made by writing to the inppgavoll/r register bits. minimum and maximum gain the mingain and maxgain register sets the minimum/maximum gain value that the pga can be set to whilst under the control of the alc. this has no effect on the pga when alc is not enabled. peak limiter to prevent clipping when a large signal occurs just after a period of quiet, the alc circuit includes a limiter function. if the adc input signal exceeds 87.5% of full scale (?1.16db), the pga gain is ramped down at the maximum attack rate (as when alcatk = 0000), until the signal level falls below 87.5% of full scale. this function is automatically enabled whenever the alc is enabled.
wm8980 pre-production w pp rev 3.1 march 2007 42 (note: if alcatk = 0000, then the limiter makes no difference to the operation of the alc. it is designed to prevent clipping when long attack times are used). noise gate when the signal is very quiet and consists mainly of noise, the alc function may cause ?noise pumping?, i.e. loud hissing noise during silence periods. the wm8980 has a noise gate function that prevents noise pumping by comparing the signal level at the input pins against a noise gate threshold, ngth. the noise gate cuts in when: signal level at adc [dbfs] < ngth [dbfs] + pga gain [db] + mic boost gain [db] this is equivalent to: signal level at input pin [dbfs] < ngth [dbfs] the pga gain is then held constant (preventing it from ramping up as it normally would when the signal is quiet). the table below summarises the noise gate control register. the ngth control bits set the noise gate threshold with respect to the adc full-scale range. the threshold is adjusted in 6db steps. levels at the extremes of the range may cause inappropriate operation, so care should be taken with set?up of the function. the noise gate only operates in conjunction with the alc and cannot be used in limiter mode. register address bit label default description 2:0 ngth 000 noise gate threshold: 000=-39db 001=-45db 010=-51db ? (6db steps) 111=-81db r35 alc noise gate control 3 ngen 0 noise gate function enable 1 = enable 0 = disable table 21 alc noise gate control output signal path the wm8980 output signal paths consist of digital application filters, up-sampling filters, stereo hi-fi dacs, analogue mixers, speaker, stereo headphone and stereo line/mono/midrail output drivers. the digital filters and dac are enabled by register bits dacenl and dacenr. the mixers and output drivers can be separately enabled by individual control bits (see analogue outputs). thus it is possible to utilise the analogue mixing and amplification provided by the wm8980, irrespective of whether the dacs are enabled or not. the wm8980 dacs receive digital input data on the dacdat pin. the digital filter block processes the data to provide the following functions: ? digital volume control ? graphic equaliser ? digital peak limiter. ? sigma-delta modulation high performance sigma-delta 24-bit audio dac converts the digital data into an analogue signal.
pre-production wm8980 w pp rev 3.1 march 2007 43 figure 21 dac digital filter path the analogue outputs from the dacs can then be mixed with the aux analogue inputs and the adc analogue inputs. the mix is fed to the output drivers for headphone (lout1/rout1), speaker (lout2/rout2) or line (out3/out4). out3 and out4 have additional mixers which allow them to output different signals to the headphone and speaker outputs. digital playback (dac) path digital data is passed to the wm8980 via the flexible audio interface and is then passed through a variety of advanced digital filters (as shown in figure 21) to the hi-fi dacs. the dacs are enabled by the dacenl/r register bits. register address bit label default description 0 dacenl 0 left channel dac enable 0 = dac disabled 1 = dac enabled r3 power management 3 1 dacenr 0 right channel dac enable 0 = dac disabled 1 = dac enabled table 22 dac enable control the wm8980 also has a soft mute function, which, when enabled, gradually attenuates the volume of the digital signal to zero. when disabled, the gain will ramp back up to the digital gain setting. this function is enabled by default. to play back an audio signal, this function must first be disabled by setting the softmute bit to zero. register address bit label default description 0 dacpoll 0 left dac output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) 1 dacpolr 0 right dac output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) 2 amute 0 automute enable 0 = amute disabled 1 = amute enabled 3 dacosr128 0 dac oversampling rate select: 0=64x (lowest power) 1=128x (best snr) r10 dac control 6 softmute 0 softmute enable: 0=enabled 1=disabled table 23 dac control register the digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. the bitstream data enters the multi-bit, sigma-delta dacs, which convert it to a high quality analogue audio signal. the multi-bit dac architecture reduces high frequency noise and sensitivity to clock jitter. it also uses a dynamic element matching technique for high linearity and low distortion.
wm8980 pre-production w pp rev 3.1 march 2007 44 the dac output phase defaults to non-inverted. setting dacpoll will invert the dac output phase on the left channel and dacpolr inverts the phase on the right channel. auto-mute the dac has an auto-mute function which applies an analogue mute when 1024 consecutive zeros are detected. the mute is released as soon as a non-zero sample is detected. automute can be disabled using the amute control bit. digital hi-fi dac volume (gain) control the signal volume from each hi-fi dac can be controlled digitally. the gain and attenuation range is ?127db to 0db in 0.5db steps. the level of attenuation for an eight-bit code x is given by: 0.5 (x-255) db for 1 x 255; mute for x = 0 register address bit label default description 7:0 dacvoll [7:0] 11111111 ( 0db ) left dac digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db r11 left dac digital volume 8 dacvu not latched dac left and dac right volume do not update until a 1 is written to dacvu (in reg 11 or 12) 7:0 dacvolr [7:0] 11111111 ( 0db ) right dac digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db r12 right dac digital volume 8 dacvu not latched dac left and dac right volume do not update until a 1 is written to dacvu (in reg 11 or 12) table 24 dac digital volume control note: an additional gain of up to +12db can be added using the gain block embedded in the digital peak limiter circuit (see dac output limiter section). 5-band equaliser a 5-band graphic equaliser function which can be used to change the output frequency levels to suit the environment. this can be applied to the adc or dac path and is described in the 5-band equaliser section for further details on this feature. 3-d enhancement the wm8980 has an advanced digital 3-d enhancement feature which can be used to vary the perceived stereo separation of the left and right channels. like the 5-band equaliser this feature can be applied to either the adc record path or the dac playback path but not both simultaneously. see the 3-d stereo enhancement section for further details on this feature. dac digital output limiter the wm8980 has a digital output limiter function. the operation of this is shown in figure 22. in this diagram the upper graph shows the envelope of the input/output signals and the lower graph shows the gain characteristic.
pre-production wm8980 w pp rev 3.1 march 2007 45 figure 22 dac digital limiter operation the limiter has a programmable upper threshold which is close to 0db. referring to figure 22, in normal operation (limboost=000 => limit only) signals below this threshold are unaffected by the limiter. signals above the upper threshold are attenuated at a specific attack rate (set by the limatk register bits) until the signal falls below the threshold. the limiter also has a lower threshold 1db below the upper threshold. when the signal falls below the lower threshold the signal is amplified at a specific decay rate (controlled by limdcy register bits) until a gain of 0db is reached. both threshold levels are controlled by the limlvl register bits. the upper threshold is 0.5db above the value programmed by limlvl and the lower threshold is 0.5db below the limlvl value. volume boost the limiter has programmable upper gain which boosts signals below the threshold to compress the dynamic range of the signal and increase its perceived loudness. this operates as an alc function with limited boost capability. the volume boost is from 0db to +12db in 1db steps, controlled by the limboost register bits. the output limiter volume boost can also be used as a stand alone digital gain boost when the limiter is disabled.
wm8980 pre-production w pp rev 3.1 march 2007 46 register address bit label default description 3:0 limatk 0010 limiter attack time (per 6db gain change) for 44.1khz sampling. note that these will scale proportionally with sample rate. 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms 0110=6ms 0111=12ms 1000=24ms 1001=48ms 1010=96ms 1011 to 1111=192ms 7:4 limdcy 0011 limiter decay time (per 6db gain change) for 44.1khz sampling. note that these will scale proportionally with sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms 0110=48ms 0111=96ms 1000=192ms 1001=384ms 1010=768ms 1011 to 1111=1.536s r24 dac digital limiter control 1 8 limen 0 enable the dac digital limiter: 0=disabled 1=enabled r25 dac digital limiter control 2 3:0 limboost 0000 limiter volume boost (can be used as a stand alone volume boost when limen=0): 0000=0db 0001=+1db 0010=+2db ? (1db steps) 1011=+11db 1100=+12db 1101 to 1111=reserved
pre-production wm8980 w pp rev 3.1 march 2007 47 6:4 limlvl 000 programmable signal threshold level (determines level at which the limiter starts to operate) 000=-1db 001=-2db 010=-3db 011=-4db 100=-5db 101 to 111=-6db table 25 dac digital limiter control 5-band graphic equaliser a 5-band graphic equaliser (eq) is provided, which can be applied to the adc or dac path, together with 3d enhancement, under control of the eq3dmode register bit. register address bit label default description r18 eq control 1 8 eq3dmode 1 0 = equaliser and 3d enhancement applied to adc path 1 = equaliser and 3d enhancement applied to dac path table 26 eq and 3d enhancement dac or adc path select the equaliser consists of low and high frequency shelving filters (band 1 and 5) and three peak filters for the centre bands. each has adjustable cut-off or centre frequency, and selectable boost (+/- 12db in 1db steps). the peak filters have selectable bandwidth. register address bit label default description 4:0 eq1g 01100 (0db) band 1 gain control. see table 32 for details. r18 eq band 1 control 6:5 eq1c 01 band 1 cut-off frequency: 00=80hz 01=105hz 10=135hz 11=175hz table 27 eq band 1 control register address bit label default description 4:0 eq2g 01100 (0db) band 2 gain control. see table 32 for details. 6:5 eq2c 01 band 2 centre frequency: 00=230hz 01=300hz 10=385hz 11=500hz r19 eq band 2 control 8 eq2bw 0 band 2 bandwidth control 0=narrow bandwidth 1=wide bandwidth table 28 eq band 2 control
wm8980 pre-production w pp rev 3.1 march 2007 48 register address bit label default description 4:0 eq3g 01100 (0db) band 3 gain control. see table 32 for details. 6:5 eq3c 01 band 3 centre frequency: 00=650hz 01=850hz 10=1.1khz 11=1.4khz r20 eq band 3 control 8 eq3bw 0 band 3 bandwidth control 0=narrow bandwidth 1=wide bandwidth table 29 eq band 3 control register address bit label default description 4:0 eq4g 01100 (0db) band 4 gain control. see table 32 for details 6:5 eq4c 01 band 4 centre frequency: 00=1.8khz 01=2.4khz 10=3.2khz 11=4.1khz r21 eq band 4 control 8 eq4bw 0 band 4 bandwidth control 0=narrow bandwidth 1=wide bandwidth table 30 eq band 4 control register address bit label default description 4:0 eq5g 01100 (0db) band 5 gain control. see table 32 for details. r22 eq band 5 gain control 6:5 eq5c 01 band 5 cut-off frequency: 00=5.3khz 01=6.9khz 10=9khz 11=11.7khz table 31 eq band 5 control gain register gain 00000 +12db 00001 +11db 00010 +10db ?. (1db steps) 01100 0db 01101 -1db 11000 -12db 11001 to 11111 reserved table 32 gain register table
pre-production wm8980 w pp rev 3.1 march 2007 49 3d stereo enhancement the wm8980 has a digital 3d enhancement option to increase the perceived separation between the left and right channels. selection of 3d for record or playback is controlled by register bit eq3dmode. switching this bit from record to playback or from playback to record may only be done when adc and dac are disabled. the wm8980 control interface will only allow eq3dmode to be changed when adc and dac are disabled (ie adcenl = 0, adcenr = 0, dacenl = 0 and dacenr = 0). the depth3d setting controls the degree of stereo expansion. when 3d enhancement is used, it may be necessary to attenuate the signal by 6db to avoid limiting. register address bit label default description r41 (29h) 3d 3:0 depth3d[3:0] 0000 stereo depth 0000: 0% (minimum 3d effect) 0001: 6.67% .... 1110: 93.3% 1111: 100% (maximum 3d effect) table 33 3d stereo enhancement function analogue outputs the wm8980 has three sets of stereo analogue outputs. these are: ? lout1 and rout1 which are normally used to drive a headphone load. ? lout2 and rout2 ? normally used to drive an 8 ? btl speaker. ? out3 and out4 ? can be configured as a stereo line out (out3 is left output and out4 is right output). out4 can also be used to provide a mono mix of left and right channels. lout2, rout2, out3 and out4 are supplied from spkvdd and are capable of driving up to 1.5vrms signals as shown in figure 23. lout1 and rout1 are supplied from avdd and can only drive out a 1v rms signal (avdd/3.3). lout1, rout1, lout2 and rout2 have individual analogue volume pgas with -57db to +6db ranges. there are four output mixers in the output signal path, the left and right channel mixers which control the signals to speaker, headphone (and optionally the line outputs) and also dedicated out3 and out4 mixers. left and right output channel mixers the left and right output channel mixers are shown in figure 23. these mixers allow the aux inputs, the adc bypass and the dac left and right channels to be combined as desired. this allows a mono mix of the dac channels to be done as well as mixing in external line-in from the aux or speech from the input bypass path. the aux and bypass inputs have individual volume control from -15db to +6db and the dac volume can be adjusted in the digital domain if required. the output of these mixers is connected to both the headphone (lout1 and rout1) and speaker (lout2 and rout2) and can optionally be connected to the out3 and out4 mixers.
wm8980 pre-production w pp rev 3.1 march 2007 50 figure 23 left/right output channel mixers
pre-production wm8980 w pp rev 3.1 march 2007 51 register address bit label default description 5 dacr2lmix 0 right dac output to left output mixer 0 = not selected 1 = selected r49 output mixer control 6 dacl2rmix 0 left dac output to right output mixer 0 = not selected 1 = selected 0 dacl2lmix 1 left dac output to left output mixer 0 = not selected 1 = selected 1 bypl2lmix 0 left bypass path (from the left channel input boost output) to left output mixer 0 = not selected 1 = selected 4:2 byplmixvol 000 left bypass volume contol to output channel mixer: 000 = -15db 001 = -12db ? 101 = 0db 110 = +3db 111 = +6db 5 auxl2lmix 0 left auxilliary input to left channel output mixer: 0 = not selected 1 = selected r50 left channel output mixer control 8:6 auxlmixvol 000 aux left channel input to left mixer volume control: 000 = -15db 001 = -12db ? 101 = 0db 110 = +3db 111 = +6db
wm8980 pre-production w pp rev 3.1 march 2007 52 0 dacr2rmix 1 right dac output to right output mixer 0 = not selected 1 = selected 1 bypr2rmix 0 right bypass path (from the right channel input boost output) to right output mixer 0 = not selected 1 = selected 4:2 byprmixvol 000 right bypass volume control to output channel mixer: 000 = -15db 001 = -12db ? 101 = 0db 110 = +3db 111 = +6db 5 auxr2rmix 0 right auxiliary input to right channel output mixer: 0 = not selected 1 = selected r51 right channel output mixer control 8:6 auxrmixvol 000 aux right channel input to right mixer volume control: 000 = -15db 001 = -12db ? 101 = 0db 110 = +3db 111 = +6db 2 lmixen 0 left output channel mixer enable: 0 = disabled 1= enabled r3 power management 3 3 rmixen 0 right output channel mixer enable: 0 = disabled 1 = enabled table 34 left and right output mixer control headphone outputs (lout1 and rout1) the headphone outputs, lout1 and rout1 can drive a 16 ? or 32 ? headphone load, either through dc blocking capacitors, or dc coupled without any capacitor. each headphone output has an analogue volume control pga with a gain range of -57db to +6db as shown in figure 26.
pre-production wm8980 w pp rev 3.1 march 2007 53 figure 24 headphone outputs lout1 and rout1 register address bit label default description 7 lout1zc 0 headphone volume zero cross enable: 1 = change gain on zero cross only 0 = change gain immediately 6 lout1mute 0 left headphone output mute: 0 = normal operation 1 = mute 5:0 lout1vol 111001 left headphone output volume: 000000 = -57db ... 111001 = 0db ... 111111 = +6db r52 lout1 volume control 8 hpvu not latched lout1 and rout1 volumes do not update until a 1 is written to hpvu (in reg 52 or 53) 7 rout1zc 0 headphone volume zero cross enable: 1 = change gain on zero cross only 0 = change gain immediately 6 rout1mute 0 right headphone output mute: 0 = normal operation 1 = mute 5:0 rout1vol 111001 right headphone output volume: 000000 = -57db ... 111001 = 0db ... 111111 = +6db r53 rout1 volume control 8 hpvu not latched lout1 and rout1 volumes do not update until a 1 is written to hpvu (in reg 52 or 53) table 35 out1 volume control
wm8980 pre-production w pp rev 3.1 march 2007 54 headphone output using dc blocking capacitors: dc coupled headphone output: figure 25 recommended headphone output configurations when dc blocking capacitors are used, then their capacitance and the load resistance together determine the lower cut-off frequency, f c . increasing the capacitance lowers f c , improving the bass response. smaller capacitance values will diminish the bass response. assuming a 16 ? load and c1, c2 = 220 f: f c = 1 / 2 r l c 1 = 1 / (2 x 16 ? x 220 f) = 45 hz in the dc coupled configuration, the headphone ?ground? is connected to the vmid pin. the out3/4 pins can be configured as a dc output driver by setting the out3mute and out4mute register bit. the dc voltage on vmid in this configuration is equal to the dc offset on the lout1 and rout1 pins therefore no dc blocking capacitors are required. this saves space and material cost in portable applications. note that out3 and out4 have an optional output boost of 1.5x. when these are configured in this output boost mode (out3boost/out4boost=1) then the vmid value of these outputs will be equal to 1.5xavdd/2 and will not match the vmid of the headphone drivers. do not use the dc coupled output mode in this configuration. it is recommended to connect the dc coupled outputs only to headphones, and not to the line input of another device. although the built-in short circuit protection will prevent any damage to the headphone outputs, such a connection may be noisy, and may not function properly if the other device is grounded. speaker outputs (lout2 and rout2) the outputs lout2 and rout2 are designed to drive an 8 ? btl speaker but can optionally drive two headphone loads of 16 ? /32 ? or a line output (see headphone output and line output sections, respectively). each output has an individual volume control pga, an output boost/level shift bit, a mute and an enable as shown in figure 26. lout2 and rout2 output the left and right channel mixer outputs respectively. the rout2 signal path also has an optional invert. the amplifier used for this invert can be used to mix in the auxr signal with an adjustable gain range of -15db -> +6db. this allows a ?beep? signal to be applied only to the speaker output without affecting the hp or line outputs.
pre-production wm8980 w pp rev 3.1 march 2007 55 figure 26 speaker outputs lout2 and rout2
wm8980 pre-production w pp rev 3.1 march 2007 56 register address bit label default description 7 lout2zc 0 speaker volume zero cross enable: 1 = change gain on zero cross only 0 = change gain immediately 6 lout2mute 0 left speaker output mute: 0 = normal operation 1 = mute 5:0 lout2vol 111001 left speaker output volume: 000000 = -57db ... 111001 = 0db ... 111111 = +6db r54 lout2 (spk) volume control 8 spkvu not latched lout2 and rout2 volumes do not update until a 1 is written to spkvu (in reg 54 or 55) 7 rout2zc 0 speaker volume zero cross enable: 1 = change gain on zero cross only 0 = change gain immediately 6 rout2mute 0 right speaker output mute: 0 = normal operation 1 = mute 5:0 rout2vol 111001 right speaker output volume: 000000 = -57db ... 111001 = 0db ... 111111 = +6db r55 rout2 (spk) volume control 8 spkvu not latched lout2 and rout2 volumes do not update until a 1 is written to spkvu (in reg 54 or 55) table 36 speaker volume control the signal output on lout2/rout2 comes from the left/right mixer circuits and can be any combination of the dac output, the bypass path (output of the input boost stage) and the aux input. the lout2/rout2 volume is controlled by the lout2vol/ rout2vol register bits. gains over 0db may cause clipping if the signal is large. the lout2mute/ rout2mute register bits cause the speaker outputs to be muted (the output dc level is driven out). the output pins remain at the same dc level (dcop), so that no click noise is produced when muting or un-muting the speaker output stages also have a selectable gain boost of 1.5x (3.52db). when this boost is enabled the output dc level is also level shifted (from avdd/2 to 1.5xavdd/2) to prevent the signal from clipping. a dedicated amplifier bufdcop, as shown in figure 27, is used to perform the dc level shift operation. this buffer must be enabled using the bufdcopen register bit for this operating mode. it should also be noted that if spkvdd is not equal to or greater than 1.5xavdd this boost mode may result in signals clipping. table 38 summarises the effect of the spkboost control bits.
pre-production wm8980 w pp rev 3.1 march 2007 57 register address bit label default description r49 output control 2 spkboost 0 0 = s peaker gain = -1; dc = avdd / 2 1 = speaker gain = +1.5; dc = 1.5 x avdd / 2 r1 power management 1 8 bufdcopen 0 dedicated buffer for dc level shifting output stages when in 1.5x gain boost configuration. 0=buffer disabled 1=buffer enabled (required for 1.5x gain boost) table 37 speaker boost stage control spkboost output stage gain output dc level output stage configuration 0 1x (0db) avdd/2 inverting 1 1.5x (3.52db) 1.5xavdd/2 non-inverting table 38 output boost stage details register address bit label default description 5 muterpga2inv 0 mute input to invrout2 mixer 4 invrout2 0 invert rout2 output 3:1 beepvol 000 auxr input to rout2 inverter gain 000 = -15db ... 111 = +6db r43 beep control 0 beepen 0 0 = mute auxr beep input 1 = enable auxr beep input table 39 auxr ? rout2 beep mixer function
wm8980 pre-production w pp rev 3.1 march 2007 58 zero cross timeout a zero-cross timeout function is also provided so that if zero cross is enabled on the input or output pgas the gain will automatically update after a timeout period if a zero cross has not occurred. this is enabled by setting slowclken. the timeout period is dependent on the clock input to the digital and is equal to 2 21 * input clock period. register address bit label default description r7 additional control 0 slowclken 0 slow clock enable. used for both the jack insert detect debounce circuit and the zero cross timeout. 0 = slow clock disabled 1 = slow clock enabled table 40 timeout clock enable control out3/out4 mixers and output stages the out3/out4 pins can provide an additional stereo line output, a mono output, or a pseudo ground connection for headphones. there is a dedicated analogue mixer for out3 and one for out4 as shown in figure 28. the out3 and out4 output stages are powered from spkvdd and spkgnd. the indivi dually controllable outputs also incorporate an optional 1.5x boost and level shifting stage. figure 28 out3 and out4 mixers
pre-production wm8980 w pp rev 3.1 march 2007 59 out3 can provide a buffered midrail headphone pseudo-ground, or a left line output. out4 can provide a buffered midrail headphone pseudo-ground, a right line output, or a mono mix output. register address bit label default description 6 out3mute 0 0 = output stage outputs out3 mixer 1 = output stage muted ? drives out vmid. can be used as vmid buffer in this mode. 3 out4_2out3 0 out4 mixer output to out3 0 = disabled 1= enabled 2 bypl2out3 0 left adc input to out3 0 = disabled 1= enabled 1 lmix2out3 0 left dac mixer to out3 0 = disabled 1= enabled r56 out3 mixer control 0 ldac2out3 1 left dac output to out3 0 = disabled 1= enabled 6 out4mute 0 0 = output stage outputs out4 mixer 1 = output stage muted ? drives out vmid. can be used as vmid buffer in this mode. 5 halfsig 0 0=out4 normal output 1=out4 attenuated by 6db 4 lmix2out4 0 left dac mixer to out4 0 = disabled 1= enabled 3 ldac2out4 0 left dac to out4 0 = disabled 1= enabled 2 bypr2out4 0 right adc i nput to out4 0 = disabled 1= enabled 1 rmix2out4 0 right dac mixer to out4 0 = disabled 1= enabled r57 out4 mixer control 0 rdac2out4 1 right dac output to out4 0 = disabled 1= enabled table 41 out3/out4 mixer registers the out3 and out4 output stages each have a selectable gain boost of 1.5x (3.52db). when this boost is enabled the output dc level is also level shifted (from avdd/2 to 1.5xavdd/2) to prevent the signal from clipping. a dedicated amplifier bufdcop, as shown in figure 29, is used to perform the dc level shift operation. this buffer must be enabled using the bufdcopen register bit for this operating mode. it should also be noted that if spkvdd is not equal to or greater than 1.5xavdd this boost mode may result in signals clipping. table 38 summarises the effect of the out3boost and out4boost control bits.
wm8980 pre-production w pp rev 3.1 march 2007 60 figure 30 outputs out3 and out4 register address bit label default description 3 out3boost 0 0 = out3 output gain = -1; dc = avdd / 2 1 = out3 output gain = +1.5 dc = 1.5 x avdd / 2 r49 output control 4 out4boost 0 0 = out4 output gain = -1; dc = avdd / 2 1 = out4 output gain = +1.5 dc = 1.5 x avdd / 2 r1 power management 1 8 bufdcopen 0 dedicated buffer for dc level shifting output stages when in 1.5x gain boost configuration. 0=buffer disabled 1=buffer enabled (required for 1.5x gain boost) table 42 out3 and out4 boost stages control out3boost/ out4boost output stage gain output dc level output stage configuration 0 1x avdd/2 inverting 1 1.5x 1.5xavdd/2 non-inverting table 43 out3/out4 output boost stage details
pre-production wm8980 w pp rev 3.1 march 2007 61 output phasing the relative phases of the analogue outputs will depend upon the following factors: 1. dacpoll and dacpolr invert bits: setting these bits to 1 will invert the dac output. 2. mixer configuration: the polarity of the signal will depend upon the route through the mixer path. for example, dacl can be directly input to the out3 mixer, giving a 180 phase shift at the out3 mixer output. however, if dacl is input to the out3 mixer via the left mixer, an additional phase shift will be introduced, giving 0 phase shift at the out3 mixer output. 3. output boost set-up: when 1.5x boost is enabled on an output, no phase shift occurs. when 1.5x boost is not enabled, a 180 phase shift occurs. figure 23 shows where these phase inversions can occur in the output signal path. figure 31 output signal path phasing
wm8980 pre-production w pp rev 3.1 march 2007 62 table 44 shows the polarities of the outputs in various configurations. unless otherwise stated, polarity is shown with respect to left dac output in non-inverting mode. note that only registers relating to the mixer paths are shown here (mixer enables, volume settings, output enables etc are not shown). configuration dacpoll dacpolr invrout2 spkboost out3boost out4boost mixer path registers different from default out4 phase / mag out3 phase / mag lout1 phase / mag rout1 phase / mag lout2 phase / mag rout2 phase / mag default: stereo dac playback to lout1/rout1, lout2/rout2 and out4/out3 0 0 0 0 0 0 0 1 0 1 0 1 0 1 180 1 180 1 dacs inverted 1 1 0 0 0 0 180 1 180 1 180 1 180 1 0 1 0 1 stereo dac playback to lout1/rout1 and lout2/rout2 and out4/out3 (speaker boost enabled) 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1.5 0 1.5 stereo dac playback to lout1/rout1 and lout2/rout2 and out4/out3 (out3 and out4 boost enabled) 0 0 0 0 1 1 180 1.5 180 1.5 0 1 0 1 180 1 180 1 stereo playback to out3/out4 (dacs input to out3/out4 mixers via left/right mixers) 0 0 0 0 0 0 ldac2out3=0 rdac2out4=0 lmix2out3=1 rmix2out4=1 180 1 180 1 0 1 0 1 180 1 180 1 differential output of right bypass path via out3/out4 (phase shown relative to right bypass) 0 0 0 0 0 0 bypr2out4=1 out4_2out3=1 180 1 0 1 x x x x differential output of mono mix of dacs via lout2/rout2 (e.g. btl speaker drive) 0 0 1 0 0 0 0 1 0 1 0 1 0 1 180 1 0 1 high power speaker drive 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1.5 180 1.5 table 44 relative output phases note that differential output should not be set up by combining outputs in boost mode with outputs which are not in boost mode as this would cause a dc offset current on the outputs.
pre-production wm8980 w pp rev 3.1 march 2007 63 enabling the outputs each analogue output of the wm8980 can be separately enabled or disabled. the analogue mixer associated with each output has a separate enable. all outputs are disabled by default. to save power, unused parts of the wm8980 should remain disabled. the sleep bit should only be set on to reduce residual device currents once all the other power management bits have been set to off. outputs can be enabled at any time, but it is not recommended to do so when bufio is disabled (bufioen=0) or when bufdcop is disabled (bufdcopen=0) when configured in output boost mode, as this may cause pop noise (see ?power management? and ?applications information? sections). register address bit label default description 2 bufioen 0 unused input/output tie off buffer enable 6 out3mixen 0 out3 mixer enable 7 out4mixen 0 out4 mixer enable r1 power management 1 8 bufdcopen 0 output stage 1.5xavdd/2 driver enable 8 rout1en 0 rout1 output enable 2 7 lout1en 0 lout1 output enable 2 r2 power management 2 6 sleep 0 0 = normal device operation 1 = residual current reduced in device standby mode 2 lmixen 0 left mixer enable 3 rmixen 0 right mixer enable 4 vbufen 0 video buffer enable 5 rout2en 0 rout2 output enable 2 6 lout2en 0 lout2 output enable 2 7 out3en 0 out3 enable 2 r3 power management 3 8 out4en 0 out4 enable 2 table 45 output stages power management control notes: 1. all ?enable? bits are 1 = on, 0 = off 2. disabling the outputs does not automatically mute the output mixers. to avoid pop noise, it is recommended that the relevant mixer is muted before disabling outputs.table 46 thermal shutdown the speaker outputs can drive very large currents. to protect the wm8980 from overheating a thermal shutdown circuit is included. the thermal shutdown can be configured to produce an interrupt when the device reaches approximately 125 o c. see general purpose input/output section. register address bit label default description r49 output control 1 tsden 1 thermal shutdown enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled table 47 thermal shutdown unused analogue inputs/outputs whenever an analogue input/output is disabled, it remains connected to a voltage source (either avdd/2 or 1.5xavdd/2 as appropriate) through a resistor. this helps to prevent pop noise when the output is re-enabled. the resistance between the voltage buffer and the output pins can be controlled using the vroi control bit. the default impedance is low, so that any capacitors on the outputs can charge up quickly at start-up. if a high impedance is desired for disabled outputs, vroi can then be set to 1, increasing the resistance to about 30k ? .
wm8980 pre-production w pp rev 3.1 march 2007 64 register address bit label default description r49 0 vroi 0 vref (avdd/2 or 1.5xavdd/2) to analogue output resistance 0: approx 1k ? 1: approx 30 k ? table 48 disabled outputs to vref resistance a dedicated buffer is available for tying off unused analogue i/o pins as shown in figure 32. this buffer can be enabled using the bufioen register bit. if the spkboost, out3boost or out4boost bits are set, then the relevant outputs will be tied to the output of the dc level shift buffer at 1.5xavdd/2 when disabled. figure 32 summarises the tie-off options for the speaker and mono output pins. figure 32 unused input/output pin tie-off buffers
pre-production wm8980 w pp rev 3.1 march 2007 65 l/rout2en/ out3/4en out3boost/ out4boost/ spkboost vroi output configuration 0 0 0 1k ? tie-off to avdd/2 0 0 1 30k ? tie-off to avdd/2 0 1 0 1k ? tie-off to 1.5xavdd/2 0 1 1 30k ? tie-off to 1.5xavdd/2 1 0 x output enabled (dc level=avdd/2) 1 1 x output enabled (dc level=1.5xavdd/2) table 49 unused output pin tie-off options video buffer description the wm8980 incorporates a current mode output video buffer capable of operating from a 2.5v supply, with an input 3 rd order low pass filter (lpf) and clamp. the gain through this buffer can be programmed as 0db or 6db (=6db or 12db unloaded) via the control interface. the current mode output means that the signal swing seen at the output of the buffer will be the same as that at the connection to the receiving equipment (e.g. a tv). note that the input to the receiver should be ac coupled and terminated to 75 ? , as is standard, for best performance. figure 33 video buffer the input clamp should be enabled when using ac coupling at the input to the video buffer, using the vbclampen register bit. care should be taken with pcb layout, designing for at least 1ghz frequencies to avoid degrading performance. vias and sharp corners should be avoided and parasitic capacitance minimised on signal paths, which should be kept as short and straight as possible. the vbvdd s upply should be decoupled as close to the pin as possible. see the ?external components? section for more information. low pass filter a low pass filter is integrated at the video buffer input, which is intended to remove images in the video dac output waveform at multiples of the dac clock frequency. a 3 rd order butterworth filter is used, with the following characteristics:
wm8980 pre-production w pp rev 3.1 march 2007 66 wm8980 video buffer filter response -25 -20 -15 -10 -5 0 5 10 10 100 1000 10000 100000 frequency (khz) amplitude (db) 0db 0db qboost 6db 6db qboost -20dbv sinewave input, 0db gain setting, vbvdd=3.3v video buffer registers video buffer enable / disable and gain are controlled via the following registers: register address bit label default description r3 power management 3 4 vbufen 0 video buffer enable 0 = disabled 1 = enabled 0 vbclampen 0 video buffer clamp enable 0 = disabled 1 = enabled 1 vbgain 0 video buffer gain 0 = 0db (=6db unloaded) 1 = +6db (=12db unloaded) r40 video buffer 4 qboost 0 increases the filters q. table 50 video buffer registers
pre-production wm8980 w pp rev 3.1 march 2007 67 test waveforms figure 34 black needle pulse (full frame of white with a vertical black line) figure 35 dual needle pulse (50% grey field with closely-spaced white and black vertical lines spaced across the line scan) figure 36 multiburst (a horizontal multiburst of signals with frequencies ranging from 0.5mhz to 5.75mhz) figure 37 white needle pulse (a full frame of black with a vertical white line) current mode output the current mode output employed by the wm8980 video buffer allows vbvdd to operate at lower voltages than voltage mode video buffers, reducing power consumption, while the use of a current reference resistor close to the wm8980 ensures that the signal swing seen at the output of the buffer will be the same as that at the connection to the receiving equipment (e.g. a tv), providing excellent signal reproduction. current mode output also provides inherent short circuit protection at the signal output.
wm8980 pre-production w pp rev 3.1 march 2007 68 figure 38 video buffer with 0db gain figure 39 video buffer with 6db gain the outputs vbref and vbout are current mirrored transistors with a 5:1 ratio, so that: i vbout = 5 x i vbref . a reference resistor (187r in above examples) is used for feedback on the video buffer amplifier via the vbref pin. the output current from vbout will be split between the source termination and load termination (75r each in above examples). overall voltage gain (i.e. vbin to tv input) is calculated as follows: vbgain (r40[1]) loaded gain formula (source and load both terminated with 75r) loaded gain (vref=187r; rsource=75r; rload=75r) unloaded gain (vref=187r; rsource=75r; rload=0) 0 5 x (r load || r source ) / r vbref 0db +6db 1 10 x (r load || r source ) / r vbref +6db +12db see applications note wan-0166 for further information.
pre-production wm8980 w pp rev 3.1 march 2007 69 digital audio interfaces the audio interface has four pins: ? adcdat: adc data output ? dacdat: dac data input ? lrc: data left/right alignment clock ? bclk: bit clock, for synchronisation the clock signals bclk, and lrc can be outputs when the wm8980 operates as a master, or inputs when it is a slave (see master and slave mode operation, below). five different audio data formats are supported: ? left justified ? right justified ? i 2 s ? dsp mode a ? dsp mode b all of these modes are msb first. they are described in audio data formats, below. refer to the electrical characteristic section for timing information. master and slave mode operation the wm8980 audio interface may be configured as either master or slave. as a master interface device the wm8980 generates bclk and lrc and thus controls sequencing of the data transfer on adcdat and dacdat. to set the device to master mode register bit ms should be set high. in slave mode (ms=0), the wm8980 responds with data to clocks it receives over the digital audio interfaces. audio data formats in left justified mode, the msb is available on the first rising edge of bclk following an lrc transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles before each lrc transition. figure 40 left justified audio interface (assuming n-bit word length)
wm8980 pre-production w pp rev 3.1 march 2007 70 in right justified mode, the lsb is available on the last rising edge of bclk before a lrc transition. all other bits are transmitted before (msb first). depending on word length, bclk frequency and sample rate, there may be unused bclk cycles after each lrc transition. figure 41 right justified audio interface (assuming n-bit word length) in i 2 s mode, the msb is available on the second rising edge of bclk following a lrc transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of one sample and the msb of the next. figure 42 i 2 s audio interface (assuming n-bit word length)
pre-production wm8980 w pp rev 3.1 march 2007 71 in dsp/pcm mode, the left channel msb is available on either the 1 st (mode b) or 2 nd (mode a) rising edge of bclk (selectable by lrp) following a rising edge of lrc. right channel data immediately follows left channel data. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of the right channel data and the next sample. figure 43 dsp/pcm mode audio interface (mode a, lrp=0) figure 44 dsp/pcm mode audio interface (mode b, lrp=1)
wm8980 pre-production w pp rev 3.1 march 2007 72 register address bit label default description 0 mono 0 selects between stereo and mono device operation: 0=stereo device operation 1=mono device operation. data appears in ?left? phase of lrc 1 adclrswap 0 controls whether adc data appears in ?right? or ?left? phases of lrc clock: 0=adc data appear in ?left? phase of lrc 1=adc data appears in ?right? phase of lrc 2 daclrswap 0 controls whether dac data appears in ?right? or ?left? phases of lrc clock: 0=dac data appear in ?left? phase of lrc 1=dac data appears in ?right? phase of lrc 4:3 fmt 10 audio interface data format select: 00=right justified 01=left justified 10=i 2 s format 11= dsp/pcm mode 6:5 wl 10 word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits (see note) 7 lrp lrc clock polarity 0=normal 1=inverted r4 audio interface control 8 bcp bclk polarity 0=normal 1=inverted table 51 audio interface control note: right justified mode will only operate with a maximum of 24 bits. if 32-bit mode is selected, the device will operate in 24-bit mode. audio interface control the register bits controlling audio format, word length and master / slave mode are summarised below. the audio interfaces can be controlled individually. register bit ms selects audio interface operation in master or slave mode. in master mode bclk, and lrc are outputs. the frequency of bclk in master mode are controlled with bclkdiv. these are divided down versions of master clock. this may result in short bclk pulses at the end of a lrc if there is a non-integer ratio of bclks to lrc clo cks.
pre-production wm8980 w pp rev 3.1 march 2007 73 register address bit label default description 0 ms 0 sets the chip to be master over lrc and bclk 0=bclk and lrc clock are inputs 1=bclk and lrc clock are outputs generated by the wm8980 (master) 4:2 bclkdiv 000 configures the bclk output frequency, for use when the chip is master over bclk. 000=divide by 1 (bclk=mclk) 001=divide by 2 (bclk=mclk/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved 7:5 mclkdiv 010 sets the scaling for either the mclk or pll clock output (under control of clksel) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 r6 clock generation control 8 clksel 1 controls the source of the clock for all internal operation: 0=mclk 1=pll output table 52 clock control loopback setting the loopback register bit enables digital loopback. when this bit is set the output data from the adc audio interface is fed directly into the dac data input. companding the wm8980 supports a-law and -law and companding and linear mode on both transmit (adc) and receive (dac) sides. companding can be enabled on the dac or adc audio interfaces by writing the appropriate value to the dac_comp or adc_comp register bits respectively.
wm8980 pre-production w pp rev 3.1 march 2007 74 register address bit label default description 0 loopback 0 digital loopback function 0=no loopback 1=loopback enabled, adc data output is fed directly into dac data input. 2:1 adc_comp 0 adc companding 00=off (linear mode) 01=reserved 10=-law 11=a-law 4:3 dac_comp 0 dac companding 00=off (linear mode) 01=reserved 10=-law 11=a-law r5 companding control 5 wl8 0 companding control 8-bit mode 0=off 1=device operates in 8-bit mode table 53 companding control companding involves using a piecewise linear approximation of the following equations (as set out by itu-t g.711 standard) for data compression: -law (where =255 for the u.s. and japan): f(x) = ln( 1 + |x|) / ln( 1 + ) -1 x 1 a-law (where a=87.6 for europe): f(x) = a|x| / ( 1 + lna) } for x 1/a f(x) = ( 1 + lna|x|) / (1 + lna) } for 1/a x 1 the companded data is also inverted as recommended by the g.711 standard (all 8 bits are inverted for -law, all even data bits are inverted for a-law). the data will be transmitted as the first 8 msb?s of data. companding converts 13 bits ( -law) or 12 bits (a-law) to 8 bits using non-linear quantization. the input data range is separated into 8 levels, allowing low amplitude signals better precision than that of high amplitude signals. this is to exploit the operation of the human auditory system, where louder sounds do not require as much resolution as quieter sounds. the companded signal is an 8- bit word containing sign (1-bit), exponent (3-bits) and mantissa (4-bits). setting the wl8 register bit allows the device to operate with 8-bit data. in this mode it is possible to use 8 bclk?s per lrc frame. when using dsp mode b, this allows 8-bit data words to be output consecutively every 8 bclk?s and can be used with 8-bit data words using the a-law and u-law companding functions. bit7 bit[6:4] bit[3:0] sign exponent mantissa table 54 8-bit companded word composition
pre-production wm8980 w pp rev 3.1 march 2007 75 u-law companding 0 20 40 60 80 100 120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output figure 45 u-law companding a-law companding 0 20 40 60 80 100 120 0 0.2 0.4 0.6 0.8 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output figure 46 a-law companding
wm8980 pre-production w pp rev 3.1 march 2007 76 audio sample rates the wm8980 sample rates for the adcs and the dacs are set using the sr register bits. the cutoffs for the digital filters and the alc attack/decay times stated are determined using these values and assume a 256fs master clock rate. if a sample rate that is not explicitly supported by the sr register settings is required then the closest sr value to that sample rate should be chosen, the filter characteristics and the alc attack, decay and hold times will scale appropriately. register address bit label default description r7 additional control 3:1 sr 000 approximate sample rate (configures the coefficients for the internal digital filters): 000=48khz 001=32khz 010=24khz 011=16khz 100=12khz 101=8khz 110-111=reserved table 55 sample rate control master clock and phase locked loop (pll) the wm8980 has an on-chip phase-locked loop (pll) circuit that can be used to: ? generate master clocks for the wm8980 audio functions from another external clock, e.g. in telecoms applications. ? generate and output (on pin csb/gpio1 and/or gpi04) a clock for another part of the system that is derived from an existing audio master clock. figure 47 shows the pll and internal clocking arrangment on the wm8980. the pll can be enabled or disabled by the pllen register bit. note: in order to minimise current consumption, the pll is disabled when the vmidsel[1:0] bits are set to 00b. vmidsel[1:0] must be set to a value other than 00b to enable the pll. register address bit label default description r1 power management 1 5 pllen 0 pll enable 0=pll off 1=pll on table 56 pllen control bit
pre-production wm8980 w pp rev 3.1 march 2007 77 figure 47 pll and clock select circuit the pll frequency ratio r = f 2 /f 1 (see figure 47) can be set using the register bits pllk and plln: plln = int r pllk = int (2 24 (r-plln)) example: mclk=12mhz, required clock = 12.288mhz. r should be chosen to ensure 5 < plln < 13. there is a fixed divide by 4 in the pll and a selectable divide by n after the pll which should be set to divide by 2 to meet this requirement. enabling the divide by 2 sets the required f 2 = 4 x 2 x 12.288mhz = 98.304mhz. r = 98.304 / 12 = 8.192 plln = int r = 8 k = int ( 2 24 x (8.192 ? 8)) = 3221225 = 3126e9h register address bit label default description 4 pllprescale 0 divide mclk by 2 before input to pll r36 pll n value 3:0 plln[3:0] 1000 integer (n) part of pll input/output frequency ratio. use values greater than 5 and less than 13. r37 pll k value 1 5:0 pllk [23:18] 0ch r38 pll k value 2 8:0 pllk [17:9] 093h r39 pll k value 3 8:0 pllk [8:0] 0e9h fractional (k) part of pll1 input/output frequency ratio (treat as one 24-digit binary number). table 57 pll frequency ratio control the pll performs best when f 2 is around 90mhz. its stability peaks at n=8. some example settings are shown in table 58.
wm8980 pre-production w pp rev 3.1 march 2007 78 mclk (mhz) (f1) desired output (mhz) f2 (mhz) prescale divide postscale divide r n (hex) k (hex) 12 11.29 90.3168 1 2 7.5264 7 86c226 12 12.288 98.304 1 2 8.192 8 3126e8 13 11.29 90.3168 1 2 6.947446 6 f28bd4 13 12.288 98.304 1 2 7.561846 7 8fd525 14.4 11.29 90.3168 1 2 6.272 6 45a1ca 14.4 12.288 98.304 1 2 6.826667 6 d3a06e 19.2 11.29 90.3168 2 2 9.408 9 6872af 19.2 12.288 98.304 2 2 10.24 a 3d70a3 19.68 11.29 90.3168 2 2 9.178537 9 2db492 19.68 12.288 98.304 2 2 9.990243 9 fd809f 19.8 11.29 90.3168 2 2 9.122909 9 1f76f7 19.8 12.288 98.304 2 2 9.929697 9 ee009e 24 11.29 90.3168 2 2 7.5264 7 86c226 24 12.288 98.304 2 2 8.192 8 3126e8 26 11.29 90.3168 2 2 6.947446 6 f28bd4 26 12.288 98.304 2 2 7.561846 7 8fd525 27 11.29 90.3168 2 2 6.690133 6 boac93 27 12.288 98.304 2 2 7.281778 7 482296 table 58 pll frequency examples general purpose input/output the wm8980 has three dual purpose input/output pins and one dedicated gpio. ? csb/gpio1: csb / gpio pin ? l2/gpio2: left channel line input / headphone detection input ? r2/gpio3: right channel line input / headphone detection input ? gpio4: dedicated gpio the gpio2 and gpio3 functions are provided for use as jack detection inputs. the gpio1 and gpio4 functions are provided for use as jack detection inputs or general purpose outputs. the default configuration for the csb/gpio1 and gpio4 pins are to be inputs. when setup as an input, the csb/gpio1 pin can either be used as csb or for jack detection, depending on how the mode pin is set. if setup as an input, the gpio4 pin can also be used for jack detection. table 49 illustrates the functionality of the gpio1 and gpio4 pins when used as general purpose outputs.
pre-production wm8980 w pp rev 3.1 march 2007 79 register address bit label default description 2:0 gpio1sel 000 csb/gpio1 pin function select: 000= input (csb/jack detection: depending on mode setting) 001= reserved 010=temp ok 011=amute active 100=pll clk o/p 101=pll lock 110=logic 0 111=logic 1 3 gpio1pol 0 gpio1 polarity invert 0=non inverted 1=inverted r8 gpio control 5:4 opclkdiv 00 pll output clock division ratio 00=divide by 1 01=divide by 2 10=divide by 3 11=divide by 4 2:0 gpio4sel 000 gpio4 pin function select: 000= input jack detection 001= reserved 010=temp ok 011=amute active 100=pll clk o/p 101=pll lock 110=logic 0 1 in reg map? 111=logic 1 0 in reg map? r9 gpio control 3 gpio4pol 0 gpio4 polarity invert 0=non inverted 1=inverted table 59 csb/gpio control note: if mode is set to 3 wire mode, csb/gpio1 shall be used as csb input irrespective of the gpio1sel[2:] bits. note that slowclken must be enabled when using the jack detect function. for further details of the jack detect operation see the output switching section. output switching (jack detect) when the device is configured with a 2-wire interface the csb/gpio1 pin can be used as a switch control input to automatically disable one set of outputs and enable another. the l2/gpio2, r2/gpio3 and gpio4 pins can also be used for this purpose. for example, when a headphone is plugged into a jack socket then it may be desirable to disable the speaker (e.g. when one of the gpio pins is connected to a mechanical switch in the headphone socket to detect plug-in). the gpio pins have an internal de-bounce circuit when in this mode in order to prevent the output enables from toggling multiple times due to input glitches. this de-bounce circuit is clocked from a slow clock with period 2 21 x mclk. note that slowclken must be enabled when using the jack detect function. note that the gpiopol bits are not relevant for jack detection, it is the signal detected at the pin which is used.
wm8980 pre-production w pp rev 3.1 march 2007 80 the switching on/off of the outputs is fully configurable by the user. each output, out1, out2, out3 and out4 has 2 associated enables. out1_en_0, out2_en_0, out3_en_0 and out4_en_0 are the output enable signal which are used if the selected jack detection pin is at logic 0 (after de-bounce). out1_en_1, out2_en_1, out3_en_1 and out4_en_1 are the output enable signals which are used if the selected jack detection pin is at logic 1 (after de-bounce). similar to the output enables, vmid, which can be driven out of out3 can be configured to be on/off depending on the jack detection input polarity using the vmid_en_0 and vmid_en_1 bits. the jack detection enables work as follows: all out_en signals have an and function performed with their normal enable signals (in table 45). when an output is normally enabled at per table 45, the selected jack detection enable (controlled by selected jack detection pin polarity) is set 0, it will turn the output off. if the normal enable signal is already off (0), the jack detection signal will have no effect due on the and function. during jack detection if the user desires an output to be un-changed whether the jack is in or not, both the jd_en settings i.e. jd_en0 and jd_en1, should be set to 0000. the vmid_en signal has an or function performed with the normal vmid driver enable. if the vmid_en signal is to have no effect to normal functionality when jack detection is enabled, it should set to 0 for all jd_en0 or jd_en1 settings. if jack detection is not enabled (jd_en=0), the output enables default to all 1?s, allowing the outputs to be controlled as normal via the normal output enables found in table 45. similarly the vmid_en signal defaults to 0 allowing the vmid driver to be controlled via the normal enable bit. register address bit label default description 5:4 jd_sel 00 pin selected as jack detection input 00 = gpio1 01 = gpio2 10 = gpio3 11 = gpio4 6 jd_en 0 jack detection enable 0=disabled 1=enabled r9 gpio control 8:7 jd_vmid 00 [7] vmid_en_0 [8] vmid_en_1 3:0 jd_en0 0 output enabled when selected jack detection input is logic 0. [0]= out1_en_0 [1]= out2_en_0 [2]= out3_en_0 [3]= out4_en_0 r13 gpw control 7:4 jd_en1 0 output enabled when selected jack detection input is logic 1 [4]= out1_en_1 [5]= out2_en_1 [6]= out3_en_1 [7]= out4_en_1 table 60 jack detect register control bits
pre-production wm8980 w pp rev 3.1 march 2007 81 control interface selection of control mode and 2-wire mode address the control interface can operate as either a 3-wire or 2-wire mpu interface. the mode pin determines the 2 or 3 wire mode as shown in table 61. the wm8980 is controlled by writing to registers through a serial control interface. a control word consists of 16 bits. the first 7 bits (b15 to b9) are address bits that select which control register is accessed. the remaining 9 bits (b8 to b0) are register bits, corresponding to the 9 bits in each control register. mode interface format low 2 wire high 3 wire table 61 control interface mode selection 3-wire serial control mode in 3-wire mode, every rising edge of sclk clocks in one data bit from the sdin pin. a rising edge on csb/gpio1 pin latches in a complete control word consisting of the last 16 bits. figure 48 3-wire serial control interface 2-wire serial control mode the wm8980 supports software control via a 2-wire serial bus. many devices can be controlled by the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit address of each register in the wm8980). the wm8980 operates as a slave 2-wire device only. the controller indicates the start of data transfer with a high to low transition on sdin while sclk remains high. this indicates that a device address and data will follow. all devices on the 2-wire bus respond to the start condition and shift in the next eight bits on sdin (7-bit address + read/write bit, msb first). if the device address received matches the address of the wm8980, then the wm8980 responds by pulling sdin low on the next clock pulse (ack). if the address is not recognised or the r/w bit is ?1? when operating in write only mode, the wm8980 returns to the idle condition and wait for a new start condition and valid address. during a write, once the wm8980 has acknowledged a correct address, the controller sends the first byte of control data (b15 to b8, i.e. the wm8980 register address plus the first bit of register data). the wm8980 then acknowledges the first data byte by pulling sdin low for one clock pulse. the controller then sends the second byte of control data (b7 to b0, i.e. the remaining 8 bits of register data), and the wm8980 acknowledges again by pulling sdin low. transfers are complete when there is a low to high transition on sdin while sclk is high. after a complete sequence the wm8980 returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. sdin changes while sclk is high), the device jumps to the idle condition.
wm8980 pre-production w pp rev 3.1 march 2007 82 sdin sclk register address and 1st register data bit device address (7 bits) rd / wr bit ack (low) control byte 1 (bits 15 to 8) control byte 1 (bits 7 to 0) remaining 8 bits of register data stop start ack (low) ack (low) figure 49 2-wire serial control interface in 2-wire mode the wm8980 has a fixed device address, 0011010. resetting the chip the wm8980 can be reset by performing a write of any value to the software reset register (address 0 hex). this will cause all register values to be reset to their default values. in addition to this there is a power-on reset (por) circuit which ensures that the registers are set to default when the device is powered up. power supplies the wm8980 can use up to five separate power supplies: ? avdd and agnd: analogue supply, powers all analogue functions except the speaker output and mono output drivers. avdd can range from 2.5v to 3.6v and has the most significant impact on overall power consumption (except for power consumed in the headphone). a large avdd slightly improves audio quality. ? spkvdd and spkgnd: h eadphone and speaker supplies, power the speaker and mono output drivers. spkvdd can r ange from 2.5v to 5v. spkvdd can be tied to avdd, but it requires separate layout and decoupling capacitors to curb harmonic distortion. with a larger spkvdd, louder headphone and speaker outputs can be achieved with lower distortion. if spkvdd is lower than avdd, the output signal may be clipped. ? dcvdd: digital core supply, powers all digital functions except the audio and control interfaces. dcvdd can range from 1.71v to 3.6v, and has no effect on audio quality. the return path for dcvdd is dgnd, which is shared with dbvdd. ? dbvdd can range from 1.71v to 3.6v. dbvdd return path is through dgnd. ? vbvdd and vbgnd: supplies for video buffer circuit. vbvdd can r ange from 2.5v to 3.6v. it is possible to use the same supply voltage for all four supplies. however, digital and analogue supplies should be routed and decoupled separately on the pcb to keep digital switching noise out of the analogue signal paths. dcvdd should be greater than or equal to 1.9v when using the pll. recommended power up/down seqence in order to minimise output ?pop? and ?click? noise it is recommended that the device is powered up in a controlled sequence. in addition to this it is recommended that the zero cross functions are used when changing the volume in the pgas.
pre-production wm8980 w pp rev 3.1 march 2007 83 power management saving power by reducing oversampling rate the default mode of operation of the adc and dac digital filters is in 64x oversampling mode. under the control of adcosr and dacosr the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device. register address bit label default description r10 dac control 3 dacosr128 0 dac oversample rate select 0 = 64x (lowest power) 1 = 128x (best snr) r14 adc control 3 adcosr128 0 adc oversample rate select 0 = 64x (lowest power) 1 = 128x (best snr) table 62 adc and dac oversampling rate selection vmid the analogue circuitry will not work when vmid is disabled (vmidsel[1:0] = 00b). the impedance of the vmid resistor string, together with the decoupling capacitor on the vmid pin will determine the startup time of the vmid circuit. register address bit label default description r1 power management 1 1:0 vmidsel 00 reference string impedance to vmid pin (detemines startup time): 00=off (open circuit) 01=75k ? 10=300k ? 11=5k ? (for fastest startup) table 63 vmid impedance control biasen the analogue amplifiers will not operate unless bi asen is enabled. register address bit label default description r1 power management 1 3 biasen 0 analogue amplifier bias control 0=disabled 1=enabled table 64 analogue bias control
wm8980 pre-production w pp rev 3.1 march 2007 84 register map addr b[15:9] def?t val dec hex register name b8 b7 b6 b5 b4 b3 b2 b1 b0 (hex) 0 00 software reset software reset 1 01 power manage?t 1 bufdcop en out4mix en out3mix en pllen micben biasen bufioen vmidsel 000 2 02 power manage?t 2 rout1en lout1en sleep boost enr boost enl inppga enr inppga enl adcenr adcenl 000 3 03 power manage?t 3 out4en out3en lout2en rout2en vbufen rmixen lmixen dacenr dacenl 000 4 04 audio interface bcp lrp wl fmt dac lrswap adc lrswap mono 050 5 05 companding ctrl 0 0 0 wl8 dac_comp adc_comp loopback 000 6 06 clock gen ctrl clksel mclkdiv bclkdiv 0 ms 140 7 07 additional ctrl 0 0 0 0 0 sr slowclken 000 8 08 gpio stuff 0 0 0 opclkdiv gpio1pol gpio1sel[2:0] 000 9 09 jack detect control jd_vmid jd_en jd_sel gpio4pol gpio4sel[2:0] 000 10 0a dac control 0 0 soft mute 0 0 dacosr 128 amute dacpolr dacpoll 000 11 0b left dac digital vol dacvu dacvoll 0ff 12 0c right dac dig?l vol dacvu dacvolr 0ff 13 0d jack detect control jd_en1 jd_en0 000 14 0e adc control hpfen hpfapp hpfcut adcosr 128 0 adcrpol adclpol 100 15 0f left adc digital vol adcvu adcvoll 0ff 16 10 right adc digital vol adcvu adcvolr 0ff 18 12 eq1 ? low shelf eq3dmode 0 eq1c eq1g 12c 19 13 eq2 ? peak 1 eq2bw 0 eq2c eq2g 02c 20 14 eq3 ? peak 2 eq3bw 0 eq3c eq3g 02c 21 15 eq4 ? peak 3 eq4bw 0 eq4c eq4g 02c 22 16 eq5 ? high shelf 0 0 eq5c eq5g 02c 24 18 dac limiter 1 limen limdcy limatk 032 25 19 dac limiter 2 0 0 limlvl limboost 000 27 1b notch filter 1 nfu nfen nfa0[13:7] 000 28 1c notch filter 2 nfu 0 nfa0[6:0] 000 29 1d notch filter 3 nfu 0 nfa1[13:7] 000 30 1e notch filter 4 nfu 0 nfa1[6:0] 000 32 20 alc control 1 alcsel 0 alcmaxgain alcmingain 038 33 21 alc control 2 0 alchld alclvl 00b 34 22 alc control 3 alcmode alcdcy alcatk 032 35 23 noise gate 0 0 0 0 0 ngen ngth 000 36 24 pll n 0 0 0 0 pllpre scale plln[3:0] 008 37 25 pll k 1 0 0 0 pllk[23:18] 00c 38 26 pll k 2 pllk[17:9] 093 39 27 pll k 3 pllk[8:0] 0e9 40 28 video buffer 0 0 0 0 qboost 0 0 vbgain vbclamp en 000 41 29 3d control 0 0 0 0 0 depth3d 000 43 2b beep control 0 0 0 muter pga2inv invrout2 beepvol beepen 000 44 2c input ctrl mbvsel 0 r2_2 inppga rin2 inppga rip2 inppga 0 l2_2 inppga lin2 inppga lip2 inppga 033
pre-production wm8980 w pp rev 3.1 march 2007 85 45 2d left inp pga gain ctrl inppga update inppgazcl inppga mutel inppgavoll 010 46 2e right inp pga gain ctrl inpga update inppgazcr inppga muter inppgavolr 010 47 2f left adc boost ctrl pgaboostl 0 l2_2boostvol 0 auxl2boostvol 100 48 30 right adc boost ctrl pgaboostr 0 r2_2boostvol 0 auxr2boostvol 100 49 31 output ctrl 0 0 dacl2 rmix dacr2 lmix out4 boost out3 boost spk boost tsden vroi 002 50 32 left mixer ctrl auxlmixvol auxl2lmix byplmixvol bypl2lmix dacl2lmix 001 51 33 right mixer ctrl auxrmixvol auxr2rmix byprmixvol bypr2rmix dacr2rmix 001 52 34 lout1 (hp) volume ctrl hpvu lout1zc lout1 mute lout1vol 039 53 35 rout1 (hp) volume ctrl hpvu rout1zc rout1 mute rout1vol 039 54 36 lout2 (spk) volume ctrl spkvu lout2zc lout2 mute lout2vol 039 55 37 rout2 (spk) volume ctrl spkvu rout2zc rout2 mute rout2vol 039 56 38 out3 mixer ctrl 0 0 out3 mute 0 0 out4_ 2out3 bypl2 out3 lmix2 out3 ldac2 out3 001 57 39 out4 (mono) mixer ctrl 0 0 out4 mute halfsig lmix2 out4 ldac2 out4 bypr2 out4 rmix2 out4 rdac2 out4 001 table 65 wm8980 register map
wm8980 pre-production w pp rev 3.1 march 2007 86 register bits by address notes: 1. default values of n/a indicate non-latched data bits (e.g. software reset or volume update bits). 2. register bits marked as "reserved" should not be changed from the default. register address bit label default description refer to 0 (00h) [8:0] reset n/a software reset resetting the chip 8 bufdcopen 0 dedicated buffer for dc level shifting output stages when in 1.5x gain boost configuration. 0=buffer disabled 1=buffer enabled (required for 1.5x gain boost) analogue outputs 7 out4mixen 0 out4 mixer enable 0=disabled 1=enabled power management 6 out3mixen 0 out3 mixer enable 0=disabled 1=enabled power management 5 pllen 0 pll enable 0=pll off 1=pll on master clock and phase locked loop (pll) 4 micben 0 microphone bias enable 0 = off (high impedance output) 1 = on input signal path 3 biasen 0 anal ogue amplifier bias control 0=disabled 1=enabled power management 2 bufioen 0 unused input/output tie off buffer enable 0=disabled 1=enabled power management 1 (01h) 1:0 vmidsel 00 reference string impedance to vmid pin 00=off (open circuit) 01=75k ? 10=300k ? 11=5k ? power management 8 rout1en 0 rout1 output enable 0=disabled 1=enabled power management 7 lout1en 0 lout1 output enable 0=disabled 1=enabled power management 6 sleep 0 0 = normal device operation 1 = residual current reduced in device standby mode power management 5 boostenr 0 right channel input boost enable 0 = boost stage off 1 = boost stage on power management 4 boostenl 0 left channel input boost enable 0 = boost stage off 1 = boost stage on power management 2 (02h) 3 inppgaenr 0 right channel input pga enable 0 = disabled 1 = enabled power management
pre-production wm8980 w pp rev 3.1 march 2007 87 register address bit label default description refer to 2 inppgaenl 0 left channel input pga enable 0 = disabled 1 = enabled power management 1 adcenr 0 enable adc right channel: 0 = adc disabled 1 = adc enabled analogue to digital converter (adc) 0 adcenl 0 enable adc left channel: 0 = adc disabled 1 = adc enabled analogue to digital converter (adc) 8 out4en 0 out4 enable 0 = disabled 1 = enabled power management 7 out3en 0 out3 enable 0 = disabled 1 = enabled power management 6 lout2en 0 lout2 enable 0 = disabled 1 = enabled power management 5 rout2en 0 rout2 enable 0 = disabled 1 = enabled power management 4 vbufen 0 video buffer enable 0 = disabled 1 = enabled video buffer 3 rmixen 0 right output channel mixer enable: 0 = disabled 1 = enabled analogue outputs 2 lmixen 0 left output channel mixer enable: 0 = disabled 1 = enabled analogue outputs 1 dacenr 0 right channel dac enable 0 = dac disabled 1 = dac enabled analogue outputs 3 (03h) 0 dacenl 0 left channel dac enable 0 = dac disabled 1 = dac enabled analogue outputs
wm8980 pre-production w pp rev 3.1 march 2007 88 register address bit label default description refer to 8 bcp 0 bclk polarity 0=normal 1=inverted digital audio interfaces 7 lrp 0 lrc clock polarity 0=normal 1=inverted digital audio interfaces 6:5 wl 10 word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits digital audio interfaces 4:3 fmt 10 audio interface data format select: 00=right justified 01=left justified 10=i 2 s format 11= dsp/pcm mode digital audio interfaces 2 daclrswap 0 controls whether dac data appears in ?right? or ?left? phases of lrc clock: 0=dac data appear in ?left? phase of lrc 1=dac data appears in ?right? phase of lrc digital audio interfaces 1 adclrswap 0 controls whether adc data appears in ?right? or ?left? phases of lrc clock: 0=adc data appear in ?left? phase of lrc 1=adc data appears in ?right? phase of lrc digital audio interfaces 4 (04h) 0 mono 0 selects between stereo and mono device operation: 0=stereo device operation 1=mono device operation. data appears in ?left? phase of lrc digital audio interfaces 8:6 000 reserved 5 wl8 0 companding control 8-bit mode 0=off 1=device operates in 8-bit mode digital audio interfaces 4:3 dac_comp 00 dac companding 00=off (linear mode) 01=reserved 10=-law 11=a-law digital audio interfaces 2:1 adc_comp 00 adc companding 00=off (linear mode) 01=reserved 10=-law 11=a-law digital audio interfaces 5 (05h) 0 loopback 0 digital loo pback function 0=no loopback 1=loopback enabled, adc data output is fed directly into dac data input. digital audio interfaces
pre-production wm8980 w pp rev 3.1 march 2007 89 register address bit label default description refer to 8 clksel 1 controls the source of the clock for all internal operation: 0=mclk 1=pll output digital audio interfaces 7:5 mclkdiv 010 sets the scaling for either the mclk or pll clock output (under control of clksel) 000=divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 digital audio interfaces 4:2 bclkdiv 000 configures the bclk output frequency, for use when the chip is master over bclk. 000=divide by 1 (bclk=mclk) 001=divide by 2 (bclk=mclk/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved digital audio interfaces 1 0 reserved 6 (06h) 0 ms 0 sets the chip to be master over lrc and bclk 0=bclk and lrc clock are inputs 1=bclk and lrc clock are outputs generated by the wm8980 (master) digital audio interfaces 8:4 00000 reserved 3:1 sr 000 approximate sample rate (configures the coefficients for the internal digital filters): 000=48khz 001=32khz 010=24khz 011=16khz 100=12khz 101=8khz 110-111=reserved audio sample rates 7 (07h) 0 slowclken 0 slow clock enable. used for both the jack insert detect debounce circuit and the zero cross timeout. 0 = slow clock disabled 1 = slow clock enabled analogue outputs 8:6 000 reserved 5:4 opclkdiv 00 pll output clock division ratio 00=divide by 1 01=divide by 2 10=divide by 3 11=divide by 4 general purpose input/output (gpio) 8 (08h) 3 gpio1pol 0 gpio1 polarity invert 0=non inverted 1=inverted general purpose input/output (gpio)
wm8980 pre-production w pp rev 3.1 march 2007 90 register address bit label default description refer to 2:0 gpio1sel [2:0] 000 csb/gpio1 pin function select: 000= input (csb/jack detection: depending on mode setting) 001= reserved 010=temp ok 011=amute active 100=pll clk o/p 101=pll lock 110=logic 1 111=logic 0 general purpose input/output (gpio) 8:7 jd_vmid 00 [7] vmid_en_0 [8] vmid_en_1 output switching (jack detect) 6 jd_en 0 jack detection enable 0=disabled 1=enabled output switching (jack detect) 5:4 jd_sel 00 pin selected as jack detection input 00 = gpio1 01 = gpio2 10 = gpio3 11 = gpio4 output switching (jack detect) 3 gpio4pol 0 gpio4 polarity invert 0=non inverted 1=inverted general purpose input/output (gpio) 9 (09h) 2:0 gpio4sel [2:0] 000 gpio4 pin function select: 000= input jack detection 001= reserved 010=temp ok 011=amute active 100=pll clk o/p 101=pll lock 110=logic 1 111=logic 0 general purpose input/output (gpio) 8:7 00 reserved 6 softmute 0 softmute enable: 0=disabled 1=enabled output signal path 5:4 00 reserved 3 dacosr128 0 dac oversample rate select 0 = 64x (lowest power) 1 = 128x (best snr) power management 2 amute 0 automute enable 0 = amute disabled 1 = amute enabled output signal path 1 dacpolr 0 right dac output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) output signal path 10 (0ah) 0 dacpoll 0 left dac output polarity: 0 = non-inverted 1 = inverted (180 degrees phase shift) output signal path
pre-production wm8980 w pp rev 3.1 march 2007 91 register address bit label default description refer to 8 dacvu n/a dac left and dac right volume do not update until a 1 is written to dacvu (in reg 11 or 12) digital to analogue converter (dac) 11 (0bh) 7:0 dacvoll 11111111 left dac digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db digital to analogue converter (dac) 8 dacvu n/a dac left and dac right volume do not update until a 1 is written to dacvu (in reg 11 or 12) output signal path 12 (0ch) 7:0 dacvolr 11111111 right dac digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db output signal path 8 0 reserved 7:4 jd_en1 0000 output enabled when selected jack detection input is logic 1 [4]= out1_en_1 [5]= out2_en_1 [6]= out3_en_1 [7]= out4_en_1 output switching (jack detect) 13 (0dh) 3:0 jd_en0 0000 output enabled when selected jack detection input is logic 0. [0]= out1_en_0 [1]= out2_en_0 [2]= out3_en_0 [3]= out4_en_0 output switching (jack detect) 8 hpfen 1 high pass filter enable 0=disabled 1=enabled analogue to digital converter (adc) 7 hpfapp 0 select audio mode or application mode 0=audio mode (1 st order, fc = ~3.7hz) 1=application mode (2 nd order, fc = hpfcut) analogue to digital converter (adc) 6:4 hpfcut 000 application mode cut-off frequency see table 17 for details. analogue to digital converter (adc) 3 adcosr 128 0 adc oversample rate select 0 = 64x (lowest power) 1 = 128x (best snr) power management 2 0 reserved 1 adcrpol 0 adc right channel polarity adjust: 0=normal 1=inverted analogue to digital converter (adc) 14 (0eh) 0 adclpol 0 adc left channel polarity adjust: 0=normal 1=inverted analogue to digital converter (adc)
wm8980 pre-production w pp rev 3.1 march 2007 92 register address bit label default description refer to 8 adcvu n/a adc left and adc right volume do not update until a 1 is written to adcvu (in reg 16 or 17) analogue to digital converter (adc) 15 (0fh) 7:0 adcvoll 11111111 left adc digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db analogue to digital converter (adc) 8 adcvu n/a adc left and adc right volume do not update until a 1 is written to adcvu (in reg 16 or 17) analogue to digital converter (adc) 16 (10h) 7:0 adcvolr 11111111 right adc digital volume control 0000 0000 = digital mute 0000 0001 = -127db 0000 0010 = -126.5db ... 0.5db steps up to 1111 1111 = 0db analogue to digital converter (adc) 8 eq3dmode 1 0 = equaliser and 3d enhancement applied to adc path 1 = equaliser and 3d enhancement applied to dac path output signal path 7 0 reserved 6:5 eq1c eq band 1 cut-off frequency: 00=80hz 01=105hz 10=135hz 11=175hz output signal path 18 (12h) 4:0 eq1g 01100 eq band 1 gain control. see table 32 for details. output signal path 8 eq2bw 0 eq band 2 bandwidth control 0=narrow bandwidth 1=wide bandwidth output signal path 7 0 reserved output signal path 6:5 eq2c 01 eq band 2 centre frequency: 00=230hz 01=300hz 10=385hz 11=500hz output signal path 19 (13h) 4:0 eq2g 01100 eq band 2 gain control. see table 32 for details. output signal path 8 eq3bw 0 eq band 3 bandwidth control 0=narrow bandwidth 1=wide bandwidth output signal path 7 0 reserved output signal path 6:5 eq3c 01 eq band 3 centre frequency: 00=650hz 01=850hz 10=1.1khz 11=1.4khz output signal path 20 (14h) 4:0 eq3g 01100 eq band 3 gain control. see table 32 for details. output signal path
pre-production wm8980 w pp rev 3.1 march 2007 93 register address bit label default description refer to 8 eq4bw 0 eq band 4 bandwidth control 0=narrow bandwidth 1=wide bandwidth output signal path 7 0 reserved output signal path 6:5 eq4c 01 eq band 4 centre frequency: 00=1.8khz 01=2.4khz 10=3.2khz 11=4.1khz output signal path 21 (15h) 4:0 eq4g 01100 eq band 4 gain control. see table 32 for details. output signal path 8:7 0 reserved output signal path 6:5 eq5c 01 eq band 5 cut-off frequency: 00=5.3khz 01=6.9khz 10=9khz 11=11.7khz output signal path 22 (16h) 4:0 eq5g 01100 eq band 5 gain control. see table 32 for details. output signal path 8 limen 0 enable the dac digital limiter: 0=disabled 1=enabled output signal path 7:4 limdcy 0011 dac limiter decay time (per 6db gain change) for 44.1khz sampling. note that these will scale with sample rate: 0000=750us 0001=1.5ms 0010=3ms 0011=6ms 0100=12ms 0101=24ms 0110=48ms 0111=96ms 1000=192ms 1001=384ms 1010=768ms 1011 to 1111=1.536s output signal path 24 (18h) 3:0 limatk 0010 dac limiter attack time (per 6db gain change) for 44.1khz sampling. note that these will scale with sample rate. 0000=94us 0001=188s 0010=375us 0011=750us 0100=1.5ms 0101=3ms 0110=6ms 0111=12ms 1000=24ms 1001=48ms 1010=96ms 1011 to 1111=192ms output signal path
wm8980 pre-production w pp rev 3.1 march 2007 94 register address bit label default description refer to 8:7 00 reserved 6:4 limlvl 000 programmable signal threshold level (determines level at which the dac limiter starts to operate) 000=-1db 001=-2db 010=-3db 011=-4db 100=-5db 101 to 111=-6db output signal path 25 (19h) 3:0 limboost 0000 dac limiter volume boost (can be used as a stand alone volume boost when limen=0): 0000=0db 0001=+1db 0010=+2db ? (1db steps) 1011=+11db 1100=+12db 1101 to 1111=reserved output signal path 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. analogue to digital converter (adc) 7 nfen 0 notch filter enable: 0=disabled 1=enabled analogue to digital converter (adc) 27 (1bh) 6:0 nfa0[13:7] 0000000 notch filter a0 coefficient, bits [13:7] analogue to digital converter (adc) 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. analogue to digital converter (adc) 7 0 reserved 28 (1ch) 6:0 nfa0[6:0] 0000000 notch filter a0 coefficient, bits [6:0] analogue to digital converter (adc) 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. analogue to digital converter (adc) 7 0 reserved 29 (1dh) 6:0 nfa1[13:7] 0000000 notch filter a1 coefficient, bits [13:7] analogue to digital converter (adc) 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. analogue to digital converter (adc) 7 0 reserved 30 (1eh) 6:0 nfa1[6:0] 0000000 notch filter a1 coefficient, bits [6:0] analogue to digital converter (adc)
pre-production wm8980 w pp rev 3.1 march 2007 95 register address bit label default description refer to 8:7 alcsel 00 alc function select: 00=alc off 01=alc right only 10=alc left only 11=alc both on input limiter/ automatic level control (alc) 6 0 reserved 5:3 alcmaxgain 111 set maximum gain of pga 111=+35.25db 110=+29.25db 101=+23.25db 100=+17.25db 011=+11.25db 010=+5.25db 001=-0.75db 000=-6.75db input limiter/ automatic level control (alc) 32 (20h) 2:0 alcmingain 000 set minimum gain of pga 000=-12db 001=-6db 010=0db 011=+6db 100=+12db 101=+18db 110=+24db 111=+30db input limiter/ automatic level control (alc) 7:4 alchld 0000 alc hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ? (time doubles with every step) 1111 = 43.691s input limiter/ automatic level control (alc) 33 (21h) 3:0 alclvl 1011 alc target ? sets signal level at adc input 1111 : -1.5dbfs 1110 : -1.5dbfs 1101 : -3dbfs 1100 : -4.5dbfs ...... (-1.5db steps) 0001 : -21dbfs 0000 : -22.5dbfs input limiter/ automatic level control (alc) 8 alcmode 0 determines the alc mode of operation: 0=alc mode 1=limiter mode input limiter/ automatic level control (alc) decay (gain ramp-up) time (alcmode ==0) per step per 6db 90% of range 0000 410us 3.3ms 24ms 0001 820us 6.6ms 48ms 0010 1.64ms 13.1ms 192ms ? (time doubles with every step) 0011 1010 or higher 420ms 3.36s 24.576s decay (gain ramp-up) time (alcmode ==1) 34 (22h) 7:4 alcdcy [3:0] 0011 per step per 6db 90% of range input limiter/ automatic level control (alc)
wm8980 pre-production w pp rev 3.1 march 2007 96 register address bit label default description refer to 0000 90.8us 726.4us 5.26ms 0001 181.6us 1.453ms 10.53ms 0010 363.2us 2.905ms 21.06ms ? (time doubles with every step) 1010 93ms 744ms 5.39s alc attack (gain ramp-down) time (alcmode == 0) per step per 6db 90% of range 0000 104us 832us 6ms 0001 208us 1.664ms 12ms 0010 416us 3.328ms 24.1ms ? (time doubles with every step) 0010 1010 or higher 106ms 852ms 6.18s alc attack (gain ramp-down) time (alcmode == 1) per step per 6db 90% of range 0000 22.7us 182.4us 1.31ms 0001 45.4us 363.2us 2.62ms 0010 90.8us 726.4us 5.26ms ? (time doubles with every step) 3:0 alcatk 0010 1010 23.2ms 186ms 1.348s input limiter/ automatic level control (alc) 8:4 00000 reserved 3 ngen 0 alc noise gate function enable 1 = enable 0 = disable input limiter/ automatic level control (alc) 35 (23h) 2:0 ngth 000 alc noise gate threshold: 000=-39db 001=-45db 010=-51db ? (6db steps) 111=-81db input limiter/ automatic level control (alc) 8:5 0000 reserved 4 pll prescale 0 divide mclk by 2 before input to pll master clock and phase locked loop (pll) 36 (24h) 3:0 plln[3:0] 1000 integer (n) part of pll input/output frequency ratio. use values greater than 5 and less than 13. master clock and phase locked loop (pll) 8:6 000 reserved 37 (25h) 5:0 pllk[23:18] 01100 fractional (k) part of pll1 input/output frequency ratio (treat as one 24-digit binary number). master clock and phase locked loop (pll) 38 (26h) 8:0 pllk[17:9] 01 0010011 fracti onal (k) part of pll1 input/output frequency ratio (treat as one 24-digit binary number). master clock and phase locked loop (pll)
pre-production wm8980 w pp rev 3.1 march 2007 97 register address bit label default description refer to 39 (27h) 8:0 pllk[8:0] 01 1101001 fracti onal (k) part of pll1 input/output frequency ratio (treat as one 24-digit binary number). master clock and phase locked loop (pll) 8:2 000000 reserved 4 qboost 0 increases ?q? of video filter video buffer 1 vbgain 0 video buffer gain 0 = 0db (=6db unloaded) 1 = +6db (=12db unloaded) video buffer 40 (28h) 0 vbclampen 0 video buffer clamp enable 0 = disabled 1 = enabled video buffer 8:4 00000 reserved 41 (29h) 3:0 depth3d 0000 stereo depth 0000: 0% (minimum 3d effect) 0001: 6.67% .... 1110: 93.3% 1111: 100% (maximum 3d effect) 3d stereo enhancement 8:6 000 reserved 5 muterpga 2inv 0 mute input to invrout2 mixer analogue outputs 4 invrout2 0 invert rout2 output analogue outputs 3:1 beepvol 000 auxr input to rout2 inverter gain 000 = -15db ... 111 = +6db analogue outputs 43 (2bh) 0 beepen 0 0 = mute auxr beep input 1 = enable auxr beep input analogue outputs 8 mbvsel 0 micr ophone bias voltage control 0 = 0.9 * avdd 1 = 0.6 * avdd input signal path 7 0 reserved 6 r2_2inp pga 0 connect r2 pin to right channel input pga positive terminal. 0=r2 not connected to input pga 1=r2 connected to input pga amplifier positive terminal (constant input impedance). input signal path 5 rin2inp pga 1 connect rin pin to right channel input pga negative terminal. 0=rin not connected to input pga 1=rin connected to right channel input pga amplifier negative terminal. input signal path 4 rip2inp pga 1 connect rip pin to right channel input pga amplifier positive terminal. 0 = rip not connected to input pga 1 = right channel input pga amplifier positive terminal connected to rip (constant input impedance) input signal path 44 (2ch) 3 0 reserved
wm8980 pre-production w pp rev 3.1 march 2007 98 register address bit label default description refer to 2 l2_2inp pga 0 connect l2 pin to left channel input pga positive terminal. 0=l2 not connected to input pga 1=l2 connected to input pga amplifier positive terminal (constant input impedance). input signal path 1 lin2inp pga 1 connect lin pin to left channel input pga negative terminal. 0=lin not connected to input pga 1=lin connected to input pga amplifier negative terminal. input signal path 0 lip2inp pga 1 connect lip pin to left channel input pga amplifier positive terminal. 0 = lip not connected to input pga 1 = input pga amplifier positive terminal connected to lip (constant input impedance) input signal path 8 inppga update n/a inppgavoll and inppgavolr volume do not update until a 1 is written to inppgaupdate (in reg 45 or 46) input signal path 7 inppgazcl 0 left channel input pga zero cross enable: 0=update gain when gain register changes 1=update gain on 1 st zero cross after gain register write. input signal path 6 inppga mutel 0 mute control for left channel input pga: 0=input pga not muted, normal operation 1=input pga muted (and disconnected from the following input boost stage). input signal path 45 (2dh) 5:0 inppga voll 010000 left channel input pga volume 000000 = -12db 000001 = -11.25db . 010000 = 0db . 111111 = 35.25db input signal path 8 inppga update n/a inppgavoll and inppgavolr volume do not update until a 1 is written to inppgaupdate (in reg 45 or 46) input signal path 7 inppga zcr 0 right channel input pga zero cross enable: 0=update gain when gain register changes 1=update gain on 1 st zero cross after gain register write. input signal path 6 inppga muter 0 mute control for right channel input pga: 0=input pga not muted, normal operation 1=input pga muted (and disconnected from the following input boost stage). input signal path 46 (2eh) 5:0 inppga volr 010000 right channel input pga volume 000000 = -12db 000001 = -11.25db . 010000 = 0db . 111111 = +35.25db input signal path 47 (2fh) 8 pga boostl 1 boost enable for left channel input pga: 0 = pga output has +0db gain through input boost stage. 1 = pga output has +20db gain through input boost stage. input signal path
pre-production wm8980 w pp rev 3.1 march 2007 99 register address bit label default description refer to 7 0 reserved 6:4 l2_2 boostvol 000 controls the l2 pin to the left channel input boost stage: 000=path disabled (disconnected) 001=-12db gain through boost stage 010=-9db gain through boost stage ? 111=+6db gain through boost stage input signal path 3 0 reserved 2:0 auxl2 boostvol 000 controls the auxilliary amplifer to the left channel input boost stage: 000=path disabled (disconnected) 001=-12db gain through boost stage 010=-9db gain through boost stage ? 111=+6db gain through boost stage input signal path 8 pga boostr 1 boost enable for right channel input pga: 0 = pga output has +0db gain through input boost stage. 1 = pga output has +20db gain through input boost stage. input signal path 7 0 reserved 6:4 r2_2 boostvol 000 controls the r2 pin to the right channel input boost stage: 000=path disabled (disconnected) 001=-12db gain through boost stage 010=-9db gain through boost stage ? 111=+6db gain through boost stage input signal path 3 0 reserved 48 (30h) 2:0 auxr2 boostvol 000 controls the auxilliary amplifer to the right channel input boost stage: 000=path disabled (disconnected) 001=-12db gain through boost stage 010=-9db gain through boost stage ? 111=+6db gain through boost stage input signal path 8:7 00 reserved 6 dacl2rmix 0 left dac output to right output mixer 0 = not selected 1 = selected analogue outputs 5 dacr2lmix 0 right dac output to left output mixer 0 = not selected 1 = selected analogue outputs 4 out4 boost 0 0 = out4 output gain = -1; dc = avdd / 2 1 = out4 output gain = +1.5 dc = 1.5 x avdd / 2 analogue outputs 49 (31h) 3 out3 boost 0 0 = out3 output gain = -1; dc = avdd / 2 1 = out3 output gain = +1.5 dc = 1.5 x avdd / 2 analogue outputs
wm8980 pre-production w pp rev 3.1 march 2007 100 register address bit label default description refer to 2 spkboost 0 0 = speaker gain = -1; dc = avdd / 2 1 = speaker gain = +1.5; dc = 1.5 x avdd / 2 analogue outputs 1 tsden 1 thermal shutdown enable 0 : thermal shutdown disabled 1 : thermal shutdown enabled analogue outputs 0 vroi 0 vref (avdd/2 or 1.5xavdd/2) to analogue output resistance 0: approx 1k ? 1: approx 30 k ? analogue outputs 8:6 auxlmix vol 000 aux left channel input to left mixer volume control: 000 = -15db 001 = -12db ? 101 = 0db 110 = +3db 111 = +6db analogue outputs 5 auxl2l mix 0 left auxilliary input to left channel output mixer: 0 = not selected 1 = selected analogue outputs 4:2 byplmix vol 000 left bypass volume contol to output channel mixer: 000 = -15db 001 = -12db ? 101 = 0db 110 = +3db 111 = +6db analogue outputs 1 bypl2l mix 0 left bypass path (from the left channel input boost output) to left output mixer 0 = not selected 1 = selected analogue outputs 50 (32h) 0 dacl2l mix 1 left dac output to left output mixer 0 = not selected 1 = selected analogue outputs 8:6 auxrmix vol 000 aux right channel input to right mixer volume control: 000 = -15db 001 = -12db ? 101 = 0db 110 = +3db 111 = +6db analogue outputs 5 auxr2r mix 0 right auxilliary input to right channel output mixer: 0 = not selected 1 = selected analogue outputs 51 (33h) 4:2 byprmix vol 000 right bypass volume contol to output channel mixer: 000 = -15db 001 = -12db ? 101 = 0db 110 = +3db 111 = +6db analogue outputs
pre-production wm8980 w pp rev 3.1 march 2007 101 register address bit label default description refer to 1 bypr2r mix 0 right bypass path (from the right channel input boost output) to right output mixer 0 = not selected 1 = selected analogue outputs 0 dacr2r mix 1 right dac output to right output mixer 0 = not selected 1 = selected analogue outputs 8 hpvu n/a lout1 and rout1 volumes do not update until a 1 is written to hpvu (in reg 52 or 53) analogue outputs 7 lout1zc 0 headphone volume zero cross enable: 1 = change gain on zero cross only 0 = change gain immediately analogue outputs 6 lout1 mute 0 left headphone output mute: 0 = normal operation 1 = mute analogue outputs 52 (34h) 5:0 lout1vol 111001 left headphone output volume: 000000 = -57db ... 111001 = 0db ... 111111 = +6db analogue outputs 8 hpvu n/a lout1 and rout1 volumes do not update until a 1 is written to hpvu (in reg 52 or 53) analogue outputs 7 rout1zc 0 headphone volume zero cross enable: 1 = change gain on zero cross only 0 = change gain immediately analogue outputs 6 rout1 mute 0 right headphone output mute: 0 = normal operation 1 = mute analogue outputs 53 (35h) 5:0 rout1vol 111001 right headphone output volume: 000000 = -57db ... 111001 = 0db ... 111111 = +6db analogue outputs 8 spkvu n/a lout2 and rout2 volumes do not update until a 1 is written to spkvu (in reg 54 or 55) analogue outputs 7 lout2zc 0 speaker volume zero cross enable: 1 = change gain on zero cross only 0 = change gain immediately analogue outputs 6 lout2 mute 0 left speaker output mute: 0 = normal operation 1 = mute analogue outputs 54 (36h) 5:0 lout2vol 111001 left speaker output volume: 000000 = -57db ... 111001 = 0db ... 111111 = +6db analogue outputs 8 spkvu n/a lout2 and rout2 volumes do not update until a 1 is written to spkvu (in reg 54 or 55) analogue outputs 55 (37h) 7 rout2zc 0 speaker volume zero cross enable: 1 = change gain on zero cross only 0 = change gain immediately analogue outputs
wm8980 pre-production w pp rev 3.1 march 2007 102 register address bit label default description refer to 6 rout2 mute 0 right speaker output mute: 0 = normal operation 1 = mute analogue outputs 5:0 rout2vol 111001 right speaker output volume: 000000 = -57db ... 111001 = 0db ... 111111 = +6db analogue outputs 8:7 00 reserved 6 out3mute 0 0 = output stage outputs out3 mixer 1 = output stage muted ? drives out vmid. can be used as vmid buffer in this mode. analogue outputs 5:4 00 reserved 3 out4_2out3 0 out4 m ixer out put to out3 0 = disabled 1= enabled analogue outputs 2 bypl2out3 0 left adc input to out3 0 = disabled 1= enabled analogue outputs 1 lmix2out3 0 left dac mixer to out3 0 = disabled 1= enabled analogue outputs 56 (38h) 0 ldac2out3 1 left dac output to out3 0 = disabled 1= enabled analogue outputs 8:7 00 reserved 6 out4mute 0 0 = output stage outputs out4 mixer 1 = output stage muted ? drives out vmid. can be used as vmid buffer in this mode. analogue outputs 5 halfsig 0 0=out4 normal output 1=out4 attenuated by 6db analogue outputs 4 lmix2out4 0 left dac mixer to out4 0 = disabled 1= enabled analogue outputs 3 ldac2out4 0 left dac to out4 0 = disabled 1= enabled analogue outputs 2 bypr2out4 0 right adc i nput to out4 0 = disabled 1= enabled analogue outputs 1 rmix2out4 0 right dac mixer to out4 0 = disabled 1= enabled analogue outputs 57 (39h) 0 rdac2out4 1 right dac output to out4 0 = disabled 1= enabled analogue outputs
pre-production wm8980 w pp rev 3.1 march 2007 103 digital filter characteristics parameter test conditions min typ max unit adc filter +/- 0.025db 0 0.454fs passband -6db 0.5fs passband ripple +/- 0.025 db stopband 0.546fs stopband attenuation f > 0.546fs -60 db group delay 21/fs adc high pass filter -3db 3.7 -0.5db 10.4 high pass filter corner frequency -0.1db 21.6 hz dac filter +/- 0.035db 0 0.454fs passband -6db 0.5fs passband ripple +/-0.035 db stopband 0.546fs stopband attenuation f > 0.546fs -55 db group delay 29/fs table 66 digital filter characteristics terminology 1. stop band attenuation (db) ? the degree to which the frequency spectrum is attenuated (outside audio band) 2. pass-band ripple ? any variation of the frequency response in the pass-band region
wm8980 pre-production w pp rev 3.1 march 2007 104 dac filter responses -160 -140 -120 -100 -80 -60 -40 -20 0 20 00.5 11.5 22.5 frequency (fs) response (db) 2.6 2.65 2.7 2.75 2.8 2.85 2.9 2.95 3 3.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (fs) response (db) figure 50 dac digital filter frequency response (128xosr) figure 51 dac digital filter ripple (128xosr) -160 -140 -120 -100 -80 -60 -40 -20 0 20 00.5 11.5 22.5 frequency (fs) response (db) 2.6 2.65 2.7 2.75 2.8 2.85 2.9 2.95 3 3.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (fs) response (db) figure 52 dac digital filter frequency response (64xosr) figure 53 dac digital filter ripple (64xosr) adc filter responses -120 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 frequency (fs) response (db) -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 0.1 0.2 0.3 0.4 0.5 frequency (fs) response (db) figure 54 adc digital filter frequency response figure 55 adc digital filter ripple
pre-production wm8980 w pp rev 3.1 march 2007 105 highpass filter the wm8980 has a selectable digital highpass filter in the adc filter path. this filter has two modes, audio and applications. in audio mode the filter is a 1 st order iir with a cut-off of around 3.7hz. in applications mode the filter is a 2 nd order high pass filter with a selectable cut-off frequency. -40 -35 -30 -25 -20 -15 -10 -5 0 5 0 5 10 15 20 25 30 35 40 45 frequency (hz) response (db) figure 56 adc highpass filter response, hpfapp=0 -60 -50 -40 -30 -20 -10 0 10 0 200 400 600 800 1000 1200 frequency (hz) response (db) -80 -70 -60 -50 -40 -30 -20 -10 0 10 0 200 400 600 800 1000 1200 frequency (hz) response (db) figure 57 adc highpass filter responses (48khz), hpfapp=1, all cut-off settings shown. figure 58 adc highpass filter responses (24khz), hpfapp=1, all cut-off settings shown. -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 0 200 400 600 800 1000 1200 frequency (hz) response (db) figure 59 adc highpass filter responses (12khz), hpfapp=1, all cut-off settings shown.
wm8980 pre-production w pp rev 3.1 march 2007 106 5-band equaliser the wm8980 has a 5-band equaliser which can be applied to either the adc path or the dac path. the plots from figure 60 to figure 73 show the frequency responses of each filter with a sampling frequency of 48khz, firstly showing the different cut-off/centre frequencies with a gain of 12db, and secondly a sweep of the gain from -12db to +12db for the lowest cut-off/centre frequency of each filter. 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 60 eq band 1 low frequency shelf filter cut-offs figure 61 eq band 1 gains for lowest cut-off frequency 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 62 eq band 2 ? peak filter centre frequencies, eq2bw=0 figure 63 eq band 2 ? peak filter gains for lowest cut-off frequency, eq2bw=0 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 64 eq band 2 ? eq2bw=0, eq2bw=1
pre-production wm8980 w pp rev 3.1 march 2007 107 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 65 eq band 3 ? peak filter centre frequencies, eq3 b figure 66 eq band 3 ? peak filter gains for lowest cut-off frequency, eq3bw=0 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 67 eq band 3 ? eq3bw=0, eq3bw=1
wm8980 pre-production w pp rev 3.1 march 2007 108 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 68 eq band 4 ? peak filter centre frequencies, eq3 b figure 69 eq band 4 ? peak filter gains for lowest cut-off frequency, eq4bw=0 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 70 eq band 4 ? eq3bw=0, eq3bw=1 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) figure 71 eq band 5 high frequency shelf filter cut-offs figure 72 eq band 5 gains for lowest cut-off frequency
pre-production wm8980 w pp rev 3.1 march 2007 109 figure 73 shows the result of having the gain set on more than one channel simultaneously. the blue traces show each band (lowest cut-off/centre frequency) with 12db gain. the red traces show the cumulative effect of all bands with +12db gain and all bands -12db gain, with eqxbw=0 for the peak filters. 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 20 frequency (hz) magnitude (db) figure 73 cumulative frequency boost/cut
wm8980 pre-production w pp rev 3.1 march 2007 110 application information recommended external components figure 74 recommended external component diagram
pre-production wm8980 w pp rev 3.1 march 2007 111 package diagram dm037.b fl: 40 pin qfn plastic package 6 x 6 x 0.9 mm body, 0.50 mm lead pitch notes: 1. dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from terminal tip. 2. falls within jedec, mo-220, variation vjjd-2. 3. all dimensions are in millimetres. 4. the terminal #1 identifier and terminal numbering convention shall conform to jedec 95-1 spp-002. 5. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. refer to application note wan_0118 for further information regarding pcb footprints and qfn package soldering. 7. depending on the method of lead termination at the edge of the package, pull back (l1) may be present. 8. this drawing is subject to change without notice. a a1 a3 0.80 0.90 1.00 0.05 0.02 0 0.20 ref b d d2 e e2 e l 0.30 0.18 6.00 bsc 4.25 4.15 4.00 0.50 bsc 0.30 0.40 0.50 2 2 6.00 bsc 4.25 4.15 4.00 0.10 aaa bbb ccc ref: 0.15 0.10 jedec, mo-220, variation vjjd-2. tolerances of form and position 0.25 h 0.1 0.213 g t 0.1 w 0.2 detail 2 1 detail 1 index area (d/2 x e/2) top view d e 4 detail 1 bottom view c aaa 2 x c aaa 2 x e2 10 1 e b 1 b c bbb m a d2 a 21 30 40 31 11 20 c a3 seating plane side view detail 2 a1 c 0.08 c ccc a 5 a3 g t h b exposed lead half etch tie bar w 7 aa dd cc bb l l1 dimensions (mm) symbols min nom max note dimensions (mm) symbols min nom max note aa 0.235 l1 dd cc bb 0.15 0.03 0.181 0.181 0.235 7 7 7 7 exposed ground paddle 6
wm8980 pre-production w pp rev 3.1 march 2007 112 important notice wolfson microelectronics plc (?wolfson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at the date of shipment. wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant information from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. in order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. wolfson is not liable for applications assistance or customer product design. the customer is solely responsible for its selection and use of wolfson products. wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. any provision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party owner. reproduction of information from wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. address: wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com

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